From: Bryan Wu <pengw@nvidia.com>
To: Thierry Reding <treding@nvidia.com>
Cc: <hansverk@cisco.com>, <linux-media@vger.kernel.org>,
<ebrower@nvidia.com>, <jbang@nvidia.com>, <swarren@nvidia.com>,
<davidw@nvidia.com>, <gfitzer@nvidia.com>, <bmurthyv@nvidia.com>
Subject: Re: [PATCH 1/3] [media] v4l: tegra: Add NVIDIA Tegra VI driver
Date: Tue, 22 Sep 2015 12:05:17 -0700 [thread overview]
Message-ID: <5601A66D.9060800@nvidia.com> (raw)
In-Reply-To: <20150922114720.GB1417@ulmo.nvidia.com>
On 09/22/2015 04:47 AM, Thierry Reding wrote:
> On Mon, Sep 21, 2015 at 11:55:53AM -0700, Bryan Wu wrote:
> [...]
>> +static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable)
>> +{
>> + struct tegra_csi_device *csi = to_csi(subdev);
>> + struct tegra_channel *chan = subdev->host_priv;
>> + enum tegra_csi_port_num port_num = (chan->port & 1) ? PORT_B : PORT_A;
>> + struct tegra_csi_port *port = &csi->ports[port_num];
>> + int ret;
>> +
>> + if (enable) {
> [...]
>> + } else {
>> + u32 val = pp_read(port, TEGRA_CSI_PIXEL_PARSER_STATUS);
>> + dev_dbg(csi->dev, "TEGRA_CSI_PIXEL_PARSER_STATUS 0x%08x\n", val);
>> +
>> + val = cil_read(port, TEGRA_CSI_CIL_STATUS);
>> + dev_dbg(csi->dev, "TEGRA_CSI_CIL_STATUS 0x%08x\n", val);
>> +
>> + val = cil_read(port, TEGRA_CSI_CILX_STATUS);
>> + dev_dbg(csi->dev, "TEGRA_CSI_CILX_STATUS 0x%08x\n", val);
>> +
> I was going to apply this and give it a spin, but then git am complained
> about trailing whitespace above...
>
>> +#ifdef DEBUG
>> + val = csi_read(csi, TEGRA_CSI_DEBUG_COUNTER_0);
>> + dev_err(&csi->dev, "TEGRA_CSI_DEBUG_COUNTER_0 0x%08x\n", val);
>> +#endif
>> +
>> + pp_write(port, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND,
>> + (0xF << CSI_PP_START_MARKER_FRAME_MAX_OFFSET) |
>> + CSI_PP_DISABLE);
>> +
>> + clk_disable_unprepare(csi->clk);
>> + }
>> +
> and here, ...
>
>> +static int tegra_csi_probe(struct platform_device *pdev)
>> +{
> [...]
>> + for (i = 0; i < TEGRA_CSI_PORTS_NUM; i++) {
>> + /* Initialize the default format */
>> + csi->ports[i].format.code = TEGRA_VF_DEF;
>> + csi->ports[i].format.field = V4L2_FIELD_NONE;
>> + csi->ports[i].format.colorspace = V4L2_COLORSPACE_SRGB;
>> + csi->ports[i].format.width = TEGRA_DEF_WIDTH;
>> + csi->ports[i].format.height = TEGRA_DEF_HEIGHT;
>> +
>> + /* Initialize port register bases */
>> + csi->ports[i].pixel_parser = csi->iomem +
>> + (i & 1) * TEGRA_CSI_PORT_OFFSET;
>> + csi->ports[i].cil = csi->iomem + TEGRA_CSI_CIL_OFFSET +
> here and...
>
>> + (i & 1) * TEGRA_CSI_PORT_OFFSET;
>> + csi->ports[i].tpg = csi->iomem + TEGRA_CSI_TPG_OFFSET +
> here.
>
> Might be worth fixing those up if you'll respin anyway.
>
> Thierry
Thanks for pointing out this, I will rerun the check-patch.pl and fix
all those coding style errors.
-Bryan
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next prev parent reply other threads:[~2015-09-22 19:05 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-21 18:55 [PATCH 0/3 RFC v3] media: platform: add NVIDIA Tegra VI driver Bryan Wu
2015-09-21 18:55 ` [PATCH 1/3] [media] v4l: tegra: Add " Bryan Wu
2015-09-22 8:52 ` Hans Verkuil
2015-09-22 18:56 ` Bryan Wu
2015-09-22 11:47 ` Thierry Reding
2015-09-22 19:05 ` Bryan Wu [this message]
2015-09-21 18:55 ` [PATCH 2/3] ARM64: add tegra-vi support in T210 device-tree Bryan Wu
2015-09-22 12:17 ` Thierry Reding
[not found] ` <20150922121730.GC1417-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2015-09-23 1:26 ` Bryan Wu
2015-09-23 1:26 ` Bryan Wu
2015-09-21 18:55 ` [PATCH 3/3] Documentation: DT bindings: add VI and CSI bindings Bryan Wu
2015-09-22 12:20 ` Thierry Reding
2015-09-22 12:22 ` Thierry Reding
-- strict thread matches above, loose matches on Subject: below --
2015-11-11 19:50 [PATCH 0/3 RFC v5] media: platform: add NVIDIA Tegra VI driver Bryan Wu
2015-11-11 19:50 ` [PATCH 1/3] [media] v4l: tegra: Add " Bryan Wu
2015-11-11 19:50 ` Bryan Wu
[not found] ` <1447271448-30056-2-git-send-email-pengw-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-12-10 10:13 ` Hans Verkuil
2015-12-10 10:13 ` Hans Verkuil
2015-09-23 1:30 [PATCH 0/3 RFC v3] media: platform: add " Bryan Wu
[not found] ` <1442971834-2721-1-git-send-email-pengw-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-09-23 1:30 ` [PATCH 1/3] [media] v4l: tegra: Add " Bryan Wu
2015-09-23 1:30 ` Bryan Wu
2015-09-16 1:35 [PATCH 0/3 RFC v2] media: platform: add " Bryan Wu
2015-09-16 1:35 ` [PATCH 1/3] [media] v4l: tegra: Add " Bryan Wu
2015-09-16 9:13 ` Hans Verkuil
2015-09-21 18:46 ` Bryan Wu
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