From mboxrd@z Thu Jan 1 00:00:00 1970 From: Xing Zheng Subject: Re: [PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts Date: Thu, 24 Sep 2015 10:18:40 +0800 Message-ID: <56035D80.9080308@rock-chips.com> References: <1442478540-15068-1-git-send-email-zhengxing@rock-chips.com> <1442478540-15068-2-git-send-email-zhengxing@rock-chips.com> <3497055.MjziMiDfL7@diego> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <3497055.MjziMiDfL7@diego> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: =?UTF-8?B?SGVpa28gU3TDvGJuZXI=?= Cc: Mark Rutland , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Russell King , Pawel Moll , Ian Campbell , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Rob Herring , Kumar Gala , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-rockchip.vger.kernel.org T24gMjAxNeW5tDA55pyIMTfml6UgMTc6MTgsIEhlaWtvIFN0w7xibmVyIHdyb3RlOgo+IEFtIERv bm5lcnN0YWcsIDE3LiBTZXB0ZW1iZXIgMjAxNSwgMTY6Mjg6NTIgc2NocmllYiBYaW5nIFpoZW5n Ogo+PiBJbml0aWFsIHJlbGVhc2UgZm9yIHJrMzAzNiwgbm9kZSBkZWZpbml0aW9ucyByazMwMzYg c2RrIGJvYXJkLgo+Pgo+PiBTaWduZWQtb2ZmLWJ5OiBYaW5nIFpoZW5nPHpoZW5neGluZ0Byb2Nr LWNoaXBzLmNvbT4KPj4gLS0tCj4+Cj4+IENoYW5nZXMgaW4gdjI6IE5vbmUKPj4KPj4gICBhcmNo L2FybS9ib290L2R0cy9NYWtlZmlsZSAgICAgICB8ICAgIDEgKwo+PiAgIGFyY2gvYXJtL2Jvb3Qv ZHRzL3JrMzAzNi1zZGsuZHRzIHwgICA2MiArKysrKysrCj4+ICAgYXJjaC9hcm0vYm9vdC9kdHMv cmszMDM2LmR0c2kgICAgfCAgMzgxCj4+ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrIDMgZmlsZXMgY2hhbmdlZCwgNDQ0IGluc2VydGlvbnMoKykKPj4gICBjcmVhdGUgbW9k ZSAxMDA2NDQgYXJjaC9hcm0vYm9vdC9kdHMvcmszMDM2LXNkay5kdHMKPj4gICBjcmVhdGUgbW9k ZSAxMDA2NDQgYXJjaC9hcm0vYm9vdC9kdHMvcmszMDM2LmR0c2kKPj4KPj4gZGlmZiAtLWdpdCBh L2FyY2gvYXJtL2Jvb3QvZHRzL01ha2VmaWxlIGIvYXJjaC9hcm0vYm9vdC9kdHMvTWFrZWZpbGUK Pj4gaW5kZXggZDM5Y2U0Yi4uNDgyNjBjNCAxMDA2NDQKPj4gLS0tIGEvYXJjaC9hcm0vYm9vdC9k dHMvTWFrZWZpbGUKPj4gKysrIGIvYXJjaC9hcm0vYm9vdC9kdHMvTWFrZWZpbGUKPj4gQEAgLTUw Miw2ICs1MDIsNyBAQCBkdGItJChDT05GSUdfQVJDSF9ST0NLQ0hJUCkgKz0gXAo+PiAgIAlyazMw NjZhLWJxY3VyaWUyLmR0YiBcCj4+ICAgCXJrMzA2NmEtbWFyc2JvYXJkLmR0YiBcCj4+ICAgCXJr MzA2NmEtcmF5ZWFnZXIuZHRiIFwKPj4gKwlyazMwMzYtc2RrLmR0YiBcCj4gb3JkZXJpbmcgLi4u IHBsZWFzZSBwdXQgdGhlIHJrMzAzNiBhYm92ZSByazMwNjYgYm9hcmRzCkRvbmUuCj4KPj4gICAJ cmszMTg4LXJhZHhhcm9jay5kdGIgXAo+PiAgIAlyazMyODgtZXZiLWFjdDg4NDYuZHRiIFwKPj4g ICAJcmszMjg4LWV2Yi1yazgwOC5kdGIgXAo+PiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vYm9vdC9k dHMvcmszMDM2LXNkay5kdHMKPj4gYi9hcmNoL2FybS9ib290L2R0cy9yazMwMzYtc2RrLmR0cyBu ZXcgZmlsZSBtb2RlIDEwMDY0NAo+PiBpbmRleCAwMDAwMDAwLi45MTg3ZjkzCj4+IC0tLSAvZGV2 L251bGwKPj4gKysrIGIvYXJjaC9hcm0vYm9vdC9kdHMvcmszMDM2LXNkay5kdHMKPiBvciAicmsz MDM2LWV2Yi5kdHMiPyBXaGF0IGlzIHRoZSBhY3R1YWwgYm9hcmQgbmFtZWQ/CkRvbmUsIHVzZSBy azMwMzYtZXZiLmR0cwo+PiBAQCAtMCwwICsxLDYyIEBACj4+ICsvKgo+PiArICogQ29weXJpZ2h0 IChjKSAgMjAxNSBYaW5nIFpoZW5nPHpoZW5neGluZ0Byb2NrLWNoaXBzLmNvbT4KPiB0aGlzIHBy b2JhYmx5IHdhbnRzIGEgUm9ja2NoaXAgY29weXJpZ2h0IG5vdGljZT8KWWVzLCByZW1vdmUgdGhp cyBub3RpY2UuCj4+ICsgKgo+PiArICogVGhpcyBmaWxlIGlzIGR1YWwtbGljZW5zZWQ6IHlvdSBj YW4gdXNlIGl0IGVpdGhlciB1bmRlciB0aGUgdGVybXMKPj4gKyAqIG9mIHRoZSBHUEwgb3IgdGhl IFgxMSBsaWNlbnNlLCBhdCB5b3VyIG9wdGlvbi4gTm90ZSB0aGF0IHRoaXMgZHVhbAo+PiArICog bGljZW5zaW5nIG9ubHkgYXBwbGllcyB0byB0aGlzIGZpbGUsIGFuZCBub3QgdGhpcyBwcm9qZWN0 IGFzIGEKPj4gKyAqIHdob2xlLgo+PiArICoKPj4gKyAqICBhKSBUaGlzIGZpbGUgaXMgZnJlZSBz b2Z0d2FyZTsgeW91IGNhbiByZWRpc3RyaWJ1dGUgaXQgYW5kL29yCj4+ICsgKiAgICAgbW9kaWZ5 IGl0IHVuZGVyIHRoZSB0ZXJtcyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgYXMK Pj4gKyAqICAgICBwdWJsaXNoZWQgYnkgdGhlIEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbjsgZWl0 aGVyIHZlcnNpb24gMiBvZiB0aGUKPj4gKyAqICAgICBMaWNlbnNlLCBvciAoYXQgeW91ciBvcHRp b24pIGFueSBsYXRlciB2ZXJzaW9uLgo+PiArICoKPj4gKyAqICAgICBUaGlzIGZpbGUgaXMgZGlz dHJpYnV0ZWQgaW4gdGhlIGhvcGUgdGhhdCBpdCB3aWxsIGJlIHVzZWZ1bCwKPj4gKyAqICAgICBi dXQgV0lUSE9VVCBBTlkgV0FSUkFOVFk7IHdpdGhvdXQgZXZlbiB0aGUgaW1wbGllZCB3YXJyYW50 eSBvZgo+PiArICogICAgIE1FUkNIQU5UQUJJTElUWSBvciBGSVRORVNTIEZPUiBBIFBBUlRJQ1VM QVIgUFVSUE9TRS4gIFNlZSB0aGUKPj4gKyAqICAgICBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5z ZSBmb3IgbW9yZSBkZXRhaWxzLgo+PiArICoKPj4gKyAqICBPciwgYWx0ZXJuYXRpdmVseSwKPj4g KyAqCj4+ICsgKiAgYikgUGVybWlzc2lvbiBpcyBoZXJlYnkgZ3JhbnRlZCwgZnJlZSBvZiBjaGFy Z2UsIHRvIGFueSBwZXJzb24KPj4gKyAqICAgICBvYnRhaW5pbmcgYSBjb3B5IG9mIHRoaXMgc29m dHdhcmUgYW5kIGFzc29jaWF0ZWQgZG9jdW1lbnRhdGlvbgo+PiArICogICAgIGZpbGVzICh0aGUg IlNvZnR3YXJlIiksIHRvIGRlYWwgaW4gdGhlIFNvZnR3YXJlIHdpdGhvdXQKPj4gKyAqICAgICBy ZXN0cmljdGlvbiwgaW5jbHVkaW5nIHdpdGhvdXQgbGltaXRhdGlvbiB0aGUgcmlnaHRzIHRvIHVz ZSwKPj4gKyAqICAgICBjb3B5LCBtb2RpZnksIG1lcmdlLCBwdWJsaXNoLCBkaXN0cmlidXRlLCBz dWJsaWNlbnNlLCBhbmQvb3IKPj4gKyAqICAgICBzZWxsIGNvcGllcyBvZiB0aGUgU29mdHdhcmUs IGFuZCB0byBwZXJtaXQgcGVyc29ucyB0byB3aG9tIHRoZQo+PiArICogICAgIFNvZnR3YXJlIGlz IGZ1cm5pc2hlZCB0byBkbyBzbywgc3ViamVjdCB0byB0aGUgZm9sbG93aW5nCj4+ICsgKiAgICAg Y29uZGl0aW9uczoKPj4gKyAqCj4+ICsgKiAgICAgVGhlIGFib3ZlIGNvcHlyaWdodCBub3RpY2Ug YW5kIHRoaXMgcGVybWlzc2lvbiBub3RpY2Ugc2hhbGwgYmUKPj4gKyAqICAgICBpbmNsdWRlZCBp biBhbGwgY29waWVzIG9yIHN1YnN0YW50aWFsIHBvcnRpb25zIG9mIHRoZSBTb2Z0d2FyZS4KPj4g KyAqCj4+ICsgKiAgICAgVEhFIFNPRlRXQVJFIElTIFBST1ZJREVEICJBUyBJUyIsIFdJVEhPVVQg V0FSUkFOVFkgT0YgQU5ZIEtJTkQsCj4+ICsgKiAgICAgRVhQUkVTUyBPUiBJTVBMSUVELCBJTkNM VURJTkcgQlVUIE5PVCBMSU1JVEVEIFRPIFRIRSBXQVJSQU5USUVTCj4+ICsgKiAgICAgT0YgTUVS Q0hBTlRBQklMSVRZLCBGSVRORVNTIEZPUiBBIFBBUlRJQ1VMQVIgUFVSUE9TRSBBTkQKPj4gKyAq ICAgICBOT05JTkZSSU5HRU1FTlQuIElOIE5PIEVWRU5UIFNIQUxMIFRIRSBBVVRIT1JTIE9SIENP UFlSSUdIVAo+PiArICogICAgIEhPTERFUlMgQkUgTElBQkxFIEZPUiBBTlkgQ0xBSU0sIERBTUFH RVMgT1IgT1RIRVIgTElBQklMSVRZLAo+PiArICogICAgIFdIRVRIRVIgSU4gQU4gQUNUSU9OIE9G IENPTlRSQUNULCBUT1JUIE9SIE9USEVSV0lTRSwgQVJJU0lORwo+PiArICogICAgIEZST00sIE9V VCBPRiBPUiBJTiBDT05ORUNUSU9OIFdJVEggVEhFIFNPRlRXQVJFIE9SIFRIRSBVU0UgT1IKPj4g KyAqICAgICBPVEhFUiBERUFMSU5HUyBJTiBUSEUgU09GVFdBUkUuCj4+ICsgKi8KPj4gKwo+PiAr L2R0cy12MS87Cj4+ICsKPj4gKyNpbmNsdWRlICJyazMwMzYuZHRzaSIKPj4gKwo+PiArLyB7Cj4+ ICsJbW9kZWwgPSAiU0RLLVJLMzAzNiI7Cj4+ICsJY29tcGF0aWJsZSA9ICJzZGssc2RrLXJrMzAz NiIsICJyb2NrY2hpcCxyazMwMzYiOwo+IAltb2RlbCA9ICJSb2NrY2hpcCBSSzMwMzYtU0RLIjsK PiAJY29tcGF0aWJsZSA9ICJyb2NrY2hpcCxyazMwMzYtc2RrIiwgInJvY2tjaGlwLHJrMzAzNiI7 Cj4KPiBvcgo+Cj4gCW1vZGVsID0gIlJvY2tjaGlwIFJLMzAzNiBFdmFsdWF0aW9uIGJvYXJkIjsK PiAJY29tcGF0aWJsZSA9ICJyb2NrY2hpcCxyazMwMzYtZXZiIiwgInJvY2tjaGlwLHJrMzAzNiI7 Cj4KPiBkZXBlbmRpbmcgb24gd2hhdCB0aGUgcmVhbCBib2FyZCBpcyBsYWJlbGVkCkRvbmUuCj4+ ICt9Owo+PiArCj4+ICsmaTJjMSB7Cj4+ICsJc3RhdHVzID0gIm9rYXkiOwo+PiArCj4+ICsgICAg ICAgIGh5bTg1NjM6IGh5bTg1NjNANTEgewo+PiArCQljb21wYXRpYmxlID0gImhhb3l1LGh5bTg1 NjMiOwo+PiArCQlyZWcgPTwweDUxPjsKPj4gKwkJI2Nsb2NrLWNlbGxzID08MD47Cj4+ICsJCWNs b2NrLWZyZXF1ZW5jeSA9PDMyNzY4PjsKPj4gKwkJY2xvY2stb3V0cHV0LW5hbWVzID0gInhpbjMy ayI7Cj4+ICsJfTsKPj4gK307Cj4+IFwgTm8gbmV3bGluZSBhdCBlbmQgb2YgZmlsZQo+IG1pc3Np bmcgbmV3bGluZSBhcyBzdGF0ZWQgYWJvdmUKRG9uZS4KPj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJt L2Jvb3QvZHRzL3JrMzAzNi5kdHNpIGIvYXJjaC9hcm0vYm9vdC9kdHMvcmszMDM2LmR0c2kKPj4g bmV3IGZpbGUgbW9kZSAxMDA2NDQKPj4gaW5kZXggMDAwMDAwMC4uYjc0NTljMAo+PiAtLS0gL2Rl di9udWxsCj4+ICsrKyBiL2FyY2gvYXJtL2Jvb3QvZHRzL3JrMzAzNi5kdHNpCj4+IEBAIC0wLDAg KzEsMzgxIEBACj4+ICsvKgo+PiArICogVGhpcyBmaWxlIGlzIGR1YWwtbGljZW5zZWQ6IHlvdSBj YW4gdXNlIGl0IGVpdGhlciB1bmRlciB0aGUgdGVybXMKPj4gKyAqIG9mIHRoZSBHUEwgb3IgdGhl IFgxMSBsaWNlbnNlLCBhdCB5b3VyIG9wdGlvbi4gTm90ZSB0aGF0IHRoaXMgZHVhbAo+PiArICog bGljZW5zaW5nIG9ubHkgYXBwbGllcyB0byB0aGlzIGZpbGUsIGFuZCBub3QgdGhpcyBwcm9qZWN0 IGFzIGEKPj4gKyAqIHdob2xlLgo+PiArICoKPj4gKyAqICBhKSBUaGlzIGZpbGUgaXMgZnJlZSBz b2Z0d2FyZTsgeW91IGNhbiByZWRpc3RyaWJ1dGUgaXQgYW5kL29yCj4+ICsgKiAgICAgbW9kaWZ5 IGl0IHVuZGVyIHRoZSB0ZXJtcyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgYXMK Pj4gKyAqICAgICBwdWJsaXNoZWQgYnkgdGhlIEZyZWUgU29mdHdhcmUgRm91bmRhdGlvbjsgZWl0 aGVyIHZlcnNpb24gMiBvZiB0aGUKPj4gKyAqICAgICBMaWNlbnNlLCBvciAoYXQgeW91ciBvcHRp b24pIGFueSBsYXRlciB2ZXJzaW9uLgo+PiArICoKPj4gKyAqICAgICBUaGlzIGZpbGUgaXMgZGlz dHJpYnV0ZWQgaW4gdGhlIGhvcGUgdGhhdCBpdCB3aWxsIGJlIHVzZWZ1bCwKPj4gKyAqICAgICBi dXQgV0lUSE9VVCBBTlkgV0FSUkFOVFk7IHdpdGhvdXQgZXZlbiB0aGUgaW1wbGllZCB3YXJyYW50 eSBvZgo+PiArICogICAgIE1FUkNIQU5UQUJJTElUWSBvciBGSVRORVNTIEZPUiBBIFBBUlRJQ1VM QVIgUFVSUE9TRS4gIFNlZSB0aGUKPj4gKyAqICAgICBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5z ZSBmb3IgbW9yZSBkZXRhaWxzLgo+PiArICoKPj4gKyAqIE9yLCBhbHRlcm5hdGl2ZWx5LAo+PiAr ICoKPj4gKyAqICBiKSBQZXJtaXNzaW9uIGlzIGhlcmVieSBncmFudGVkLCBmcmVlIG9mIGNoYXJn ZSwgdG8gYW55IHBlcnNvbgo+PiArICogICAgIG9idGFpbmluZyBhIGNvcHkgb2YgdGhpcyBzb2Z0 d2FyZSBhbmQgYXNzb2NpYXRlZCBkb2N1bWVudGF0aW9uCj4+ICsgKiAgICAgZmlsZXMgKHRoZSAi U29mdHdhcmUiKSwgdG8gZGVhbCBpbiB0aGUgU29mdHdhcmUgd2l0aG91dAo+PiArICogICAgIHJl c3RyaWN0aW9uLCBpbmNsdWRpbmcgd2l0aG91dCBsaW1pdGF0aW9uIHRoZSByaWdodHMgdG8gdXNl LAo+PiArICogICAgIGNvcHksIG1vZGlmeSwgbWVyZ2UsIHB1Ymxpc2gsIGRpc3RyaWJ1dGUsIHN1 YmxpY2Vuc2UsIGFuZC9vcgo+PiArICogICAgIHNlbGwgY29waWVzIG9mIHRoZSBTb2Z0d2FyZSwg YW5kIHRvIHBlcm1pdCBwZXJzb25zIHRvIHdob20gdGhlCj4+ICsgKiAgICAgU29mdHdhcmUgaXMg ZnVybmlzaGVkIHRvIGRvIHNvLCBzdWJqZWN0IHRvIHRoZSBmb2xsb3dpbmcKPj4gKyAqICAgICBj b25kaXRpb25zOgo+PiArICoKPj4gKyAqICAgICBUaGUgYWJvdmUgY29weXJpZ2h0IG5vdGljZSBh bmQgdGhpcyBwZXJtaXNzaW9uIG5vdGljZSBzaGFsbCBiZQo+PiArICogICAgIGluY2x1ZGVkIGlu IGFsbCBjb3BpZXMgb3Igc3Vic3RhbnRpYWwgcG9ydGlvbnMgb2YgdGhlIFNvZnR3YXJlLgo+PiAr ICoKPj4gKyAqICAgICBUSEUgU09GVFdBUkUgSVMgUFJPVklERUQgIkFTIElTIiwgV0lUSE9VVCBX QVJSQU5UWSBPRiBBTlkgS0lORCwKPj4gKyAqICAgICBFWFBSRVNTIE9SIElNUExJRUQsIElOQ0xV RElORyBCVVQgTk9UIExJTUlURUQgVE8gVEhFIFdBUlJBTlRJRVMKPj4gKyAqICAgICBPRiBNRVJD SEFOVEFCSUxJVFksIEZJVE5FU1MgRk9SIEEgUEFSVElDVUxBUiBQVVJQT1NFIEFORAo+PiArICog ICAgIE5PTklORlJJTkdFTUVOVC4gSU4gTk8gRVZFTlQgU0hBTEwgVEhFIEFVVEhPUlMgT1IgQ09Q WVJJR0hUCj4+ICsgKiAgICAgSE9MREVSUyBCRSBMSUFCTEUgRk9SIEFOWSBDTEFJTSwgREFNQUdF UyBPUiBPVEhFUiBMSUFCSUxJVFksCj4+ICsgKiAgICAgV0hFVEhFUiBJTiBBTiBBQ1RJT04gT0Yg Q09OVFJBQ1QsIFRPUlQgT1IgT1RIRVJXSVNFLCBBUklTSU5HCj4+ICsgKiAgICAgRlJPTSwgT1VU IE9GIE9SIElOIENPTk5FQ1RJT04gV0lUSCBUSEUgU09GVFdBUkUgT1IgVEhFIFVTRSBPUgo+PiAr ICogICAgIE9USEVSIERFQUxJTkdTIElOIFRIRSBTT0ZUV0FSRS4KPj4gKyAqLwo+PiArCj4+ICsj aW5jbHVkZTxkdC1iaW5kaW5ncy9ncGlvL2dwaW8uaD4KPj4gKyNpbmNsdWRlPGR0LWJpbmRpbmdz L2ludGVycnVwdC1jb250cm9sbGVyL2lycS5oPgo+PiArI2luY2x1ZGU8ZHQtYmluZGluZ3MvaW50 ZXJydXB0LWNvbnRyb2xsZXIvYXJtLWdpYy5oPgo+PiArI2luY2x1ZGU8ZHQtYmluZGluZ3MvcGlu Y3RybC9yb2NrY2hpcC5oPgo+PiArI2luY2x1ZGU8ZHQtYmluZGluZ3MvY2xvY2svcmszMDM2LWNy dS5oPgo+PiArI2luY2x1ZGUgInNrZWxldG9uLmR0c2kiCj4gaW4gZ2VuZXJhbCwgcGxlYXNlIHNv cnQgbm9kZXMgYnkgcmVnaXN0ZXIgYWRkcmVzcywgc28gZm9yIGV4YW1wbGUKPgo+IAlpbnRlcnJ1 cHQtY29udHJvbGxlckAxMDEzOTAwMAo+IHNob3VsZCBiZSBiZWZvcmUKPiAJY2xvY2stY29udHJv bGxlckAyMDAwMDAwMAo+Cj4gc2FtZSBmb3IgYWxsIG90aGVyIG5vZGVzCkRvbmUuCj4+ICsKPj4g Ky8gewo+PiArCWNvbXBhdGlibGUgPSAicm9ja2NoaXAscmszMDM2IjsKPj4gKwo+PiArCWludGVy cnVwdC1wYXJlbnQgPTwmZ2ljPjsKPj4gKwo+PiArCWFsaWFzZXMgewo+PiArCQlpMmMxID0maTJj MTsKPj4gKwkJc2VyaWFsMCA9JnVhcnQwOwo+PiArCQlzZXJpYWwxID0mdWFydDE7Cj4+ICsJCXNl cmlhbDIgPSZ1YXJ0MjsKPj4gKwl9Owo+PiArCj4+ICsJbWVtb3J5IHsKPj4gKwkJZGV2aWNlX3R5 cGUgPSAibWVtb3J5IjsKPj4gKwkJcmVnID08MHg2MDAwMDAwMCAweDQwMDAwMDAwPjsKPiBvcmRl cmluZyBpcyBwb3NzaWJsZSAuLi4gdG8gZWFzZSByZWFkYWJpbGl0eSBJIHRyeSB0byBrZWVwIHRo aXMgYXMKPgo+IGNvbXBhdGlibGUgPSAuLi4KPiByZWcgPSAuLi4KPiBbb3RoZXIgcHJvcGVydGll cyBzb3J0ZWQgYWxwaGFiZXRpY2FsbHldCj4gc3RhdHVzID0gLi4uCkRvbmUuCj4+ICsJfTsKPj4g Kwo+PiArICAgICAgICBhcm0tcG11IHsKPj4gKyAgICAgICAgICAgICAgICBjb21wYXRpYmxlID0g ImFybSxjb3J0ZXgtYTctcG11IjsKPj4gKyAgICAgICAgICAgICAgICBpbnRlcnJ1cHRzID08R0lD X1NQSSA3NiBJUlFfVFlQRV9MRVZFTF9ISUdIPiwKPj4gKzxHSUNfU1BJIDc3IElSUV9UWVBFX0xF VkVMX0hJR0g+Owo+PiArICAgICAgICAgICAgICAgIGludGVycnVwdC1hZmZpbml0eSA9PCZjcHUw Piw8JmNwdTE+Owo+PiArICAgICAgICB9Owo+IHRhYnMsIG5vdCBzcGFjZXMgcGxlYXNlCkRvbmUu Cj4+ICsKPj4gKwljcHVzIHsKPj4gKwkJI2FkZHJlc3MtY2VsbHMgPTwxPjsKPj4gKwkJI3NpemUt Y2VsbHMgPTwwPjsKPj4gKwkJZW5hYmxlLW1ldGhvZCA9ICJyb2NrY2hpcCxyazMwMzYtc21wIjsK PiB0aGlzIGVuYWJsZSBtZXRob2QgaXMgbm90IHlldCBkZWZpbmVkLCBwbGVhc2UgZG9uJ3QgYWRk IGl0IHVudGlsIGFjdHVhbCBzbXAgaXMKPiBhY2NlcHRlZApEb25lLCByZW1vdmVkIGl0IG9uIHRo aXMgcGF0Y2guCj4+ICsKPj4gKwkJY3B1MDogY3B1QGYwMCB7Cj4+ICsJCQlkZXZpY2VfdHlwZSA9 ICJjcHUiOwo+PiArCQkJY29tcGF0aWJsZSA9ICJhcm0sY29ydGV4LWE3IjsKPj4gKwkJCXJlZyA9 PDB4ZjAwPjsKPj4gKwkJCW9wZXJhdGluZy1wb2ludHMgPTwKPj4gKwkJCQkvKiBLSHogICAgdVYg Ki8KPj4gKwkJCQkgODE2MDAwIDEwMDAwMDAKPj4gKwkJCT47Cj4+ICsJCQkjY29vbGluZy1jZWxs cyA9PDI+OyAvKiBtaW4gZm9sbG93ZWQgYnkgbWF4ICovCj4gYWdhaW4sIG5vdCB5ZXQgZGVmaW5l ZCB0aGVybWFsIGhhbmRsaW5nLCBzbyB0aGUgI2Nvb2xpbmctY2VsbHMgc2hvdWxkIHN0YXkgb3V0 Cj4gZm9yIG5vdwpEb25lLCByZW1vdmVkIGl0Lgo+PiArCQkJY2xvY2stbGF0ZW5jeSA9PDQwMDAw PjsKPj4gKwkJCWNsb2NrcyA9PCZjcnUgQVJNQ0xLPjsKPj4gKwkJCXJlc2V0cyA9PCZjcnUgU1JT VF9DT1JFMD47Cj4+ICsJCX07Cj4+ICsJCWNwdTE6IGNwdUBmMDEgewo+PiArCQkJZGV2aWNlX3R5 cGUgPSAiY3B1IjsKPj4gKwkJCWNvbXBhdGlibGUgPSAiYXJtLGNvcnRleC1hNyI7Cj4+ICsJCQly ZWcgPTwweGYwMT47Cj4+ICsJCQlyZXNldHMgPTwmY3J1IFNSU1RfQ09SRTE+Owo+PiArCQl9Owo+ PiArCX07Cj4+ICsKPj4gKwlhbWJhIHsKPj4gKwkJY29tcGF0aWJsZSA9ICJhcm0sYW1iYS1idXMi Owo+PiArCQkjYWRkcmVzcy1jZWxscyA9PDE+Owo+PiArCQkjc2l6ZS1jZWxscyA9PDE+Owo+PiAr CQlyYW5nZXM7Cj4+ICsKPj4gKyAgICAgICAgICAgICAgICBwZG1hOiBwZG1hQDIwMDc4MDAwIHsK Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAiYXJtLHBsMzMwIiwgImFy bSxwcmltZWNlbGwiOwo+PiArICAgICAgICAgICAgICAgICAgICAgICAgcmVnID08MHgyMDA3ODAw MCAweDQwMDA+Owo+PiArICAgICAgICAgICAgICAgICAgICAgICAgaW50ZXJydXB0cyA9PEdJQ19T UEkgMCBJUlFfVFlQRV9MRVZFTF9ISUdIPiwKPj4gKzxHSUNfU1BJIDEgSVJRX1RZUEVfTEVWRUxf SElHSD47Cj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAjZG1hLWNlbGxzID08MT47Cj4+ICsg ICAgICAgICAgICAgICAgICAgICAgICBjbG9ja3MgPTwmY3J1IEFDTEtfRE1BQzI+Owo+PiArICAg ICAgICAgICAgICAgICAgICAgICAgY2xvY2stbmFtZXMgPSAiYXBiX3BjbGsiOwo+PiArICAgICAg ICAgICAgICAgIH07Cj4gYWdhaW4gdGFicyBwbGVhc2UKRG9uZS4KPj4gKwl9Owo+PiArCj4+ICsJ eGluMjRtOiBvc2NpbGxhdG9yIHsKPj4gKwkJY29tcGF0aWJsZSA9ICJmaXhlZC1jbG9jayI7Cj4+ ICsJCWNsb2NrLWZyZXF1ZW5jeSA9PDI0MDAwMDAwPjsKPj4gKwkJY2xvY2stb3V0cHV0LW5hbWVz ID0gInhpbjI0bSI7Cj4+ICsJCSNjbG9jay1jZWxscyA9PDA+Owo+PiArCX07Cj4+ICsKPj4gKwl0 aW1lciB7Cj4+ICsJCWNvbXBhdGlibGUgPSAiYXJtLGFybXY3LXRpbWVyIjsKPj4gKwkJYXJtLGNw dS1yZWdpc3RlcnMtbm90LWZ3LWNvbmZpZ3VyZWQ7Cj4+ICsJCWludGVycnVwdHMgPTxHSUNfUFBJ IDEzIChHSUNfQ1BVX01BU0tfU0lNUExFKDQpIHwKPiBJUlFfVFlQRV9MRVZFTF9ISUdIKT4sCj4+ ICsJCQk8R0lDX1BQSSAxNCAoR0lDX0NQVV9NQVNLX1NJTVBMRSg0KSB8IElSUV9UWVBFX0xFVkVM X0hJR0gpPiwgKwkKPiAJCQo+PiAgICAgPEdJQ19QUEkgMTEgKEdJQ19DUFVfTUFTS19TSU1QTEUo NCkgfCBJUlFfVFlQRV9MRVZFTF9ISUdIKT4sICsJCQkKPj4gPEdJQ19QUEkgMTAgKEdJQ19DUFVf TUFTS19TSU1QTEUoNCkgfCBJUlFfVFlQRV9MRVZFTF9ISUdIKT47Cj4+ICsJCWNsb2NrLWZyZXF1 ZW5jeSA9PDI0MDAwMDAwPjsKPj4gKwl9Owo+PiArCj4+ICsJY3J1OiBjbG9jay1jb250cm9sbGVy QDIwMDAwMDAwIHsKPj4gKwkJY29tcGF0aWJsZSA9ICJyb2NrY2hpcCxyazMwMzYtY3J1IjsKPj4g KwkJcmVnID08MHgyMDAwMDAwMCAweDEwMDA+Owo+PiArCQlyb2NrY2hpcCxncmYgPTwmZ3JmPjsK Pj4gKwkJI2Nsb2NrLWNlbGxzID08MT47Cj4+ICsJCSNyZXNldC1jZWxscyA9PDE+Owo+PiArCQlh c3NpZ25lZC1jbG9ja3MgPTwmY3J1IFBMTF9HUExMPjsKPj4gKwkJYXNzaWduZWQtY2xvY2stcmF0 ZXMgPTw1OTQwMDAwMDA+Owo+PiArCX07Cj4+ICsKPj4gKwl1YXJ0MDogc2VyaWFsQDIwMDYwMDAw IHsKPj4gKwkJY29tcGF0aWJsZSA9ICJyb2NrY2hpcCxyazMwMzYtdWFydCIsICJzbnBzLGR3LWFw Yi11YXJ0IjsKPj4gKwkJcmVnID08MHgyMDA2MDAwMCAweDEwMD47Cj4+ICsJCWludGVycnVwdHMg PTxHSUNfU1BJIDIwIElSUV9UWVBFX0xFVkVMX0hJR0g+Owo+PiArCQlyZWctc2hpZnQgPTwyPjsK Pj4gKwkJcmVnLWlvLXdpZHRoID08ND47Cj4+ICsJCWNsb2NrLWZyZXF1ZW5jeSA9PDI0MDAwMDAw PjsKPj4gKwkJY2xvY2tzID08JmNydSBTQ0xLX1VBUlQwPiw8JmNydSBQQ0xLX1VBUlQwPjsKPj4g KwkJY2xvY2stbmFtZXMgPSAiYmF1ZGNsayIsICJhcGJfcGNsayI7Cj4+ICsJCXBpbmN0cmwtbmFt ZXMgPSAiZGVmYXVsdCI7Cj4+ICsJCXBpbmN0cmwtMCA9PCZ1YXJ0MF94ZmVyJnVhcnQwX2N0cyZ1 YXJ0MF9ydHM+Owo+IHN0YXR1cyA9ICJkaXNhYmxlZCIgYW5kIHRoZW4gaW4gdGhlIGJvYXJkLmR0 cyBhCj4KPiAmdWFydDAgewo+IAlzdGF0dXMgPSAib2theSI7Cj4gfTsKPgo+IG5vdCBldmVyeWJv ZHkgd2lsbCB3YW50IHRvIHVzZSB1YXJ0MCAuLi4gc2FtZSBpcyB0cnVlIGZvciB0aGUgb3RoZXIg dHdvIHVhcnRzLgpEb25lLgo+PiArCX07Cj4+ICsKPj4gKwl1YXJ0MTogc2VyaWFsQDIwMDY0MDAw IHsKPj4gKwkJY29tcGF0aWJsZSA9ICJyb2NrY2hpcCxyazMwMzYtdWFydCIsICJzbnBzLGR3LWFw Yi11YXJ0IjsKPj4gKwkJcmVnID08MHgyMDA2NDAwMCAweDEwMD47Cj4+ICsJCWludGVycnVwdHMg PTxHSUNfU1BJIDIxIElSUV9UWVBFX0xFVkVMX0hJR0g+Owo+PiArCQlyZWctc2hpZnQgPTwyPjsK Pj4gKwkJcmVnLWlvLXdpZHRoID08ND47Cj4+ICsJCWNsb2NrLWZyZXF1ZW5jeSA9PDI0MDAwMDAw PjsKPj4gKwkJY2xvY2tzID08JmNydSBTQ0xLX1VBUlQxPiw8JmNydSBQQ0xLX1VBUlQxPjsKPj4g KwkJY2xvY2stbmFtZXMgPSAiYmF1ZGNsayIsICJhcGJfcGNsayI7Cj4+ICsJCXBpbmN0cmwtbmFt ZXMgPSAiZGVmYXVsdCI7Cj4+ICsJCXBpbmN0cmwtMCA9PCZ1YXJ0MV94ZmVyPjsKPj4gKwl9Owo+ PiArCj4+ICsJdWFydDI6IHNlcmlhbEAyMDA2ODAwMCB7Cj4+ICsJCWNvbXBhdGlibGUgPSAicm9j a2NoaXAscmszMDM2LXVhcnQiLCAic25wcyxkdy1hcGItdWFydCI7Cj4+ICsJCXJlZyA9PDB4MjAw NjgwMDAgMHgxMDA+Owo+PiArCQlpbnRlcnJ1cHRzID08R0lDX1NQSSAyMiBJUlFfVFlQRV9MRVZF TF9ISUdIPjsKPj4gKwkJcmVnLXNoaWZ0ID08Mj47Cj4+ICsJCXJlZy1pby13aWR0aCA9PDQ+Owo+ PiArCQljbG9jay1mcmVxdWVuY3kgPTwyNDAwMDAwMD47Cj4+ICsJCWNsb2NrcyA9PCZjcnUgU0NM S19VQVJUMj4sPCZjcnUgUENMS19VQVJUMj47Cj4+ICsJCWNsb2NrLW5hbWVzID0gImJhdWRjbGsi LCAiYXBiX3BjbGsiOwo+PiArCQlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+PiArCQlwaW5j dHJsLTAgPTwmdWFydDJfeGZlcj47Cj4+ICsJfTsKPj4gKwo+PiArCXB3bTA6IHB3bUAyMDA1MDAw MCB7Cj4+ICsJCWNvbXBhdGlibGUgPSAicm9ja2NoaXAscmsyOTI4LXB3bSI7Cj4gCQljb21wYXRp YmxlID0gInJvY2tjaGlwLHJrMzAzNi1wd20iLCAicm9ja2NoaXAscmsyOTI4LXB3bSI7Cj4KPiBy azI5MjgtcHdtIG1hdGNoZXMgbm93LCBidXQgaWYgd2UgZmluZCBpc3N1ZXMgd2UgY2FuIHNpbXBs eSBjcmVhdGUgdGhlIHJrMzAzNi0KPiBwd20gaW4gdGhlIGRyaXZlciB3aXRob3V0IG5lZWRpbmcg dG8gY2hhbmdlIHRoZSBkdHMKRG9uZS4KPj4gKwkJcmVnID08MHgyMDA1MDAwMCAweDEwPjsKPj4g KwkJI3B3bS1jZWxscyA9PDM+Owo+PiArCQlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+PiAr CQlwaW5jdHJsLTAgPTwmcHdtMF9waW4+Owo+PiArCQljbG9ja3MgPTwmY3J1IFBDTEtfUFdNPjsK Pj4gKwkJY2xvY2stbmFtZXMgPSAicHdtIjsKPj4gKwkJc3RhdHVzID0gImRpc2FibGVkIjsKPj4g Kwl9Owo+PiArCj4+ICsJcHdtMTogcHdtQDIwMDUwMDEwIHsKPj4gKwkJY29tcGF0aWJsZSA9ICJy b2NrY2hpcCxyazI5MjgtcHdtIjsKPj4gKwkJcmVnID08MHgyMDA1MDAxMCAweDEwPjsKPj4gKwkJ I3B3bS1jZWxscyA9PDM+Owo+PiArCQlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+PiArCQlw aW5jdHJsLTAgPTwmcHdtMV9waW4+Owo+PiArCQljbG9ja3MgPTwmY3J1IFBDTEtfUFdNPjsKPj4g KwkJY2xvY2stbmFtZXMgPSAicHdtIjsKPj4gKwkJc3RhdHVzID0gImRpc2FibGVkIjsKPj4gKwl9 Owo+PiArCj4+ICsJcHdtMjogcHdtQDIwMDUwMDIwIHsKPj4gKwkJY29tcGF0aWJsZSA9ICJyb2Nr Y2hpcCxyazI5MjgtcHdtIjsKPj4gKwkJcmVnID08MHgyMDA1MDAyMCAweDEwPjsKPj4gKwkJI3B3 bS1jZWxscyA9PDM+Owo+PiArCQlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+PiArCQlwaW5j dHJsLTAgPTwmcHdtMl9waW4+Owo+PiArCQljbG9ja3MgPTwmY3J1IFBDTEtfUFdNPjsKPj4gKwkJ Y2xvY2stbmFtZXMgPSAicHdtIjsKPj4gKwkJc3RhdHVzID0gImRpc2FibGVkIjsKPj4gKwl9Owo+ PiArCj4+ICsJcHdtMzogcHdtQDIwMDUwMDMwIHsKPj4gKwkJY29tcGF0aWJsZSA9ICJyb2NrY2hp cCxyazI5MjgtcHdtIjsKPj4gKwkJcmVnID08MHgyMDA1MDAzMCAweDEwPjsKPj4gKwkJI3B3bS1j ZWxscyA9PDI+Owo+PiArCQlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+PiArCQlwaW5jdHJs LTAgPTwmcHdtM19waW4+Owo+PiArCQljbG9ja3MgPTwmY3J1IFBDTEtfUFdNPjsKPj4gKwkJY2xv Y2stbmFtZXMgPSAicHdtIjsKPj4gKwkJc3RhdHVzID0gImRpc2FibGVkIjsKPj4gKwl9Owo+PiAr Cj4+ICsJc3JhbTogc3JhbUAxMDA4MDAwMCB7Cj4+ICsJCWNvbXBhdGlibGUgPSAicm9ja2NoaXAs cmszMDM2LXNtcC1zcmFtIiwgIm1taW8tc3JhbSI7Cj4+ICsJCXJlZyA9PDB4MTAwODAwMDAgMHgy MDAwPjsKPj4gKwl9Owo+PiArCj4+ICsJZ2ljOiBpbnRlcnJ1cHQtY29udHJvbGxlckAxMDEzOTAw MCB7Cj4+ICsJCWNvbXBhdGlibGUgPSAiYXJtLGdpYy00MDAiOwo+PiArCQlpbnRlcnJ1cHQtY29u dHJvbGxlcjsKPj4gKwkJI2ludGVycnVwdC1jZWxscyA9PDM+Owo+PiArCQkjYWRkcmVzcy1jZWxs cyA9PDA+Owo+PiArCj4+ICsJCXJlZyA9PDB4MTAxMzkwMDAgMHgxMDAwPiwKPj4gKwkJPDB4MTAx M2EwMDAgMHgxMDAwPiwKPj4gKwkJPDB4MTAxM2MwMDAgMHgyMDAwPiwKPj4gKwkJPDB4MTAxM2Uw MDAgMHgyMDAwPjsKPj4gKwkJaW50ZXJydXB0cyA9PEdJQ19QUEkgOSAweGYwND47Cj4+ICsJfTsK Pj4gKwo+PiArCWdyZjogc3lzY29uQDIwMDA4MDAwIHsKPj4gKwkJY29tcGF0aWJsZSA9ICJyb2Nr Y2hpcCxyazMwMzYtZ3JmIiwgInN5c2NvbiI7Cj4+ICsJCXJlZyA9PDB4MjAwMDgwMDAgMHgxMDAw PjsKPj4gKwl9Owo+PiArCj4+ICsJcGluY3RybDogcGluY3RybCB7Cj4+ICsJCWNvbXBhdGlibGUg PSAicm9ja2NoaXAscmszMDM2LXBpbmN0cmwiOwo+PiArCQlyb2NrY2hpcCxncmYgPTwmZ3JmPjsK Pj4gKwkJI2FkZHJlc3MtY2VsbHMgPTwxPjsKPj4gKwkJI3NpemUtY2VsbHMgPTwxPjsKPj4gKwkJ cmFuZ2VzOwo+PiArCj4+ICsJCWdwaW8wOiBncGlvMEAyMDA3YzAwMCB7Cj4+ICsJCQljb21wYXRp YmxlID0gInJvY2tjaGlwLGdwaW8tYmFuayI7Cj4+ICsJCQlyZWcgPTwweDIwMDdjMDAwIDB4MTAw PjsKPj4gKwkJCWludGVycnVwdHMgPTxHSUNfU1BJIDM2IElSUV9UWVBFX0xFVkVMX0hJR0g+Owo+ PiArCQkJY2xvY2tzID08JmNydSBQQ0xLX0dQSU8wPjsKPj4gKwo+PiArCQkJZ3Bpby1jb250cm9s bGVyOwo+PiArCQkJI2dwaW8tY2VsbHMgPTwyPjsKPj4gKwo+PiArCQkJaW50ZXJydXB0LWNvbnRy b2xsZXI7Cj4+ICsJCQkjaW50ZXJydXB0LWNlbGxzID08Mj47Cj4+ICsJCX07Cj4+ICsKPj4gKwkJ Z3BpbzE6IGdwaW8xQDIwMDgwMDAwIHsKPj4gKwkJCWNvbXBhdGlibGUgPSAicm9ja2NoaXAsZ3Bp by1iYW5rIjsKPj4gKwkJCXJlZyA9PDB4MjAwODAwMDAgMHgxMDA+Owo+PiArCQkJaW50ZXJydXB0 cyA9PEdJQ19TUEkgMzcgSVJRX1RZUEVfTEVWRUxfSElHSD47Cj4+ICsJCQljbG9ja3MgPTwmY3J1 IFBDTEtfR1BJTzE+Owo+PiArCj4+ICsJCQlncGlvLWNvbnRyb2xsZXI7Cj4+ICsJCQkjZ3Bpby1j ZWxscyA9PDI+Owo+PiArCj4+ICsJCQlpbnRlcnJ1cHQtY29udHJvbGxlcjsKPj4gKwkJCSNpbnRl cnJ1cHQtY2VsbHMgPTwyPjsKPj4gKwkJfTsKPj4gKwo+PiArCQlncGlvMjogZ3BpbzJAMjAwODQw MDAgewo+PiArCQkJY29tcGF0aWJsZSA9ICJyb2NrY2hpcCxncGlvLWJhbmsiOwo+PiArCQkJcmVn ID08MHgyMDA4NDAwMCAweDEwMD47Cj4+ICsJCQlpbnRlcnJ1cHRzID08R0lDX1NQSSAzOCBJUlFf VFlQRV9MRVZFTF9ISUdIPjsKPj4gKwkJCWNsb2NrcyA9PCZjcnUgUENMS19HUElPMj47Cj4+ICsK Pj4gKwkJCWdwaW8tY29udHJvbGxlcjsKPj4gKwkJCSNncGlvLWNlbGxzID08Mj47Cj4+ICsKPj4g KwkJCWludGVycnVwdC1jb250cm9sbGVyOwo+PiArCQkJI2ludGVycnVwdC1jZWxscyA9PDI+Owo+ PiArCQl9Owo+PiArCj4+ICsJCXBjZmdfcHVsbF91cDogcGNmZy1wdWxsLXVwIHsKPj4gKwkJCWJp YXMtcHVsbC11cDsKPj4gKwkJfTsKPj4gKwo+PiArCQlwY2ZnX3B1bGxfZG93bjogcGNmZy1wdWxs LWRvd24gewo+PiArCQkJYmlhcy1wdWxsLWRvd247Cj4+ICsJCX07Cj4+ICsKPj4gKwkJcGNmZ19w dWxsX25vbmU6IHBjZmctcHVsbC1ub25lIHsKPj4gKwkJCWJpYXMtZGlzYWJsZTsKPj4gKwkJfTsK Pj4gKwo+PiArCQl1YXJ0MCB7Cj4+ICsJCQl1YXJ0MF94ZmVyOiB1YXJ0MC14ZmVyIHsKPj4gKwkJ CQlyb2NrY2hpcCxwaW5zID08MCAxNiBSS19GVU5DXzEmcGNmZ19wdWxsX25vbmU+LAo+IHBjZmdf cHVsbF91cCBmb3IgdGhlIHJ4LXBpbj8KRG9uZQo+PiArCQkJCQkJPDAgMTcgUktfRlVOQ18xJnBj ZmdfcHVsbF9ub25lPjsKPj4gKwkJCX07Cj4+ICsKPj4gKwkJCXVhcnQwX2N0czogdWFydDAtY3Rz IHsKPj4gKwkJCQlyb2NrY2hpcCxwaW5zID08MCAxOCBSS19GVU5DXzEmcGNmZ19wdWxsX25vbmU+ Owo+PiArCQkJfTsKPiBwY2ZnX3B1bGxfdXAgYWdhaW4/Cj4gc2VlIEFSTTogZHRzOiByb2NrY2hp cDogcHVsbCB1cCBjdHMgbGluZXMgb24gcmszMjg4Cj4gKGh0dHBzOi8vbGttbC5vcmcvbGttbC8y MDE1LzkvMi82MTIpIGZvciBjb21wYXJpc29uClllcywgdGhleSBzaG91bGQgYmUgcHVsbCB1cC4K Pgo+PiArCj4+ICsJCQl1YXJ0MF9ydHM6IHVhcnQwLXJ0cyB7Cj4+ICsJCQkJcm9ja2NoaXAscGlu cyA9PDAgMTkgUktfRlVOQ18xJnBjZmdfcHVsbF9ub25lPjsKPj4gKwkJCX07Cj4+ICsJCX07Cj4+ ICsKPj4gKwkJdWFydDEgewo+PiArCQkJdWFydDFfeGZlcjogdWFydDEteGZlciB7Cj4+ICsJCQkJ cm9ja2NoaXAscGlucyA9PDIgMjIgUktfRlVOQ18xJnBjZmdfcHVsbF9ub25lPiwKPj4gKwkJCQkJ CTwyIDIzIFJLX0ZVTkNfMSZwY2ZnX3B1bGxfbm9uZT47Cj4+ICsJCQl9Owo+PiArCQkJLyogbm8g cnRzIC8gY3RzIGZvciB1YXJ0MSAqLwo+PiArCQl9Owo+PiArCj4+ICsgICAgICAgICAgICAgICAg dWFydDIgewo+PiArICAgICAgICAgICAgICAgICAgICAgICAgdWFydDJfeGZlcjogdWFydDIteGZl ciB7Cj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJvY2tjaGlwLHBpbnMgPTwx IDE4IFJLX0ZVTkNfMgo+PiAmcGNmZ19wdWxsX25vbmU+LCArPDEgMTkKPj4gUktfRlVOQ18yJnBj ZmdfcHVsbF9ub25lPjsgKyAgICAgICAgICAgICAgICAgICAgICAgIH07Cj4+ICsgICAgICAgICAg ICAgICAgICAgICAgICAvKiBubyBydHMgLyBjdHMgZm9yIHVhcnQyICovCj4+ICsgICAgICAgICAg ICAgICAgfTsKPiB0YWJzIHBsZWFzZQpTb3JyeSwgZG9uZS4KPj4gKwo+PiArCQlwd20wIHsKPj4g KwkJCXB3bTBfcGluOiBwd20wLXBpbiB7Cj4+ICsJCQkJcm9ja2NoaXAscGlucyA9PDAgMCBSS19G VU5DXzImcGNmZ19wdWxsX25vbmU+Owo+PiArCQkJfTsKPj4gKwkJfTsKPj4gKwo+PiArCQlwd20x IHsKPj4gKwkJCXB3bTFfcGluOiBwd20xLXBpbiB7Cj4+ICsJCQkJcm9ja2NoaXAscGlucyA9PDAg MSBSS19GVU5DXzImcGNmZ19wdWxsX25vbmU+Owo+PiArCQkJfTsKPj4gKwkJfTsKPj4gKwo+PiAr CQlwd20yIHsKPj4gKwkJCXB3bTJfcGluOiBwd20yLXBpbiB7Cj4+ICsJCQkJcm9ja2NoaXAscGlu cyA9PDAgMSAyJnBjZmdfcHVsbF9ub25lPjsKPj4gKwkJCX07Cj4+ICsJCX07Cj4+ICsKPj4gKwkJ cHdtMyB7Cj4+ICsJCQlwd20zX3BpbjogcHdtMy1waW4gewo+PiArCQkJCXJvY2tjaGlwLHBpbnMg PTwwIDI3IDEmcGNmZ19wdWxsX25vbmU+Owo+PiArCQkJfTsKPj4gKwkJfTsKPj4gKwo+PiArCQlp MmMxIHsKPj4gKwkJCWkyYzFfeGZlcjogaTJjMS14ZmVyIHsKPj4gKwkJCQlyb2NrY2hpcCxwaW5z ID08MCAyIFJLX0ZVTkNfMSZwY2ZnX3B1bGxfbm9uZT4sCj4+ICsJCQkJCQk8MCAzIFJLX0ZVTkNf MSZwY2ZnX3B1bGxfbm9uZT47Cj4+ICsJCQl9Owo+PiArCQl9Owo+PiArCX07Cj4+ICsKPj4gKwlp MmMxOiBpMmNAMjAwNTYwMDAgewo+PiArCQljb21wYXRpYmxlID0gInJvY2tjaGlwLHJrMzI4OC1p MmMiOwo+PiArCQlyZWcgPTwweDIwMDU2MDAwIDB4MTAwMD47Cj4+ICsJCWludGVycnVwdHMgPTxH SUNfU1BJIDI1IElSUV9UWVBFX0xFVkVMX0hJR0g+Owo+PiArCQkjYWRkcmVzcy1jZWxscyA9PDE+ Owo+PiArCQkjc2l6ZS1jZWxscyA9PDA+Owo+PiArCQljbG9jay1uYW1lcyA9ICJpMmMiOwo+PiAr CQljbG9ja3MgPTwmY3J1IFBDTEtfSTJDMT47Cj4+ICsJCXBpbmN0cmwtbmFtZXMgPSAiZGVmYXVs dCI7Cj4+ICsJCXBpbmN0cmwtMCA9PCZpMmMxX3hmZXI+Owo+PiArCQlzdGF0dXMgPSAiZGlzYWJs ZWQiOwo+PiArCX07Cj4+ICt9Owo+ClRoYW5rcy4KCgoKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KTGludXgtcm9ja2NoaXAgbWFpbGluZyBsaXN0CkxpbnV4 LXJvY2tjaGlwQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcv bWFpbG1hbi9saXN0aW5mby9saW51eC1yb2NrY2hpcAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: zhengxing@rock-chips.com (Xing Zheng) Date: Thu, 24 Sep 2015 10:18:40 +0800 Subject: [PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts In-Reply-To: <3497055.MjziMiDfL7@diego> References: <1442478540-15068-1-git-send-email-zhengxing@rock-chips.com> <1442478540-15068-2-git-send-email-zhengxing@rock-chips.com> <3497055.MjziMiDfL7@diego> Message-ID: <56035D80.9080308@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 2015?09?17? 17:18, Heiko St?bner wrote: > Am Donnerstag, 17. September 2015, 16:28:52 schrieb Xing Zheng: >> Initial release for rk3036, node definitions rk3036 sdk board. >> >> Signed-off-by: Xing Zheng >> --- >> >> Changes in v2: None >> >> arch/arm/boot/dts/Makefile | 1 + >> arch/arm/boot/dts/rk3036-sdk.dts | 62 +++++++ >> arch/arm/boot/dts/rk3036.dtsi | 381 >> ++++++++++++++++++++++++++++++++++++++ 3 files changed, 444 insertions(+) >> create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts >> create mode 100644 arch/arm/boot/dts/rk3036.dtsi >> >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile >> index d39ce4b..48260c4 100644 >> --- a/arch/arm/boot/dts/Makefile >> +++ b/arch/arm/boot/dts/Makefile >> @@ -502,6 +502,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ >> rk3066a-bqcurie2.dtb \ >> rk3066a-marsboard.dtb \ >> rk3066a-rayeager.dtb \ >> + rk3036-sdk.dtb \ > ordering ... please put the rk3036 above rk3066 boards Done. > >> rk3188-radxarock.dtb \ >> rk3288-evb-act8846.dtb \ >> rk3288-evb-rk808.dtb \ >> diff --git a/arch/arm/boot/dts/rk3036-sdk.dts >> b/arch/arm/boot/dts/rk3036-sdk.dts new file mode 100644 >> index 0000000..9187f93 >> --- /dev/null >> +++ b/arch/arm/boot/dts/rk3036-sdk.dts > or "rk3036-evb.dts"? What is the actual board named? Done, use rk3036-evb.dts >> @@ -0,0 +1,62 @@ >> +/* >> + * Copyright (c) 2015 Xing Zheng > this probably wants a Rockchip copyright notice? Yes, remove this notice. >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This file is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This file is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +/dts-v1/; >> + >> +#include "rk3036.dtsi" >> + >> +/ { >> + model = "SDK-RK3036"; >> + compatible = "sdk,sdk-rk3036", "rockchip,rk3036"; > model = "Rockchip RK3036-SDK"; > compatible = "rockchip,rk3036-sdk", "rockchip,rk3036"; > > or > > model = "Rockchip RK3036 Evaluation board"; > compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; > > depending on what the real board is labeled Done. >> +}; >> + >> +&i2c1 { >> + status = "okay"; >> + >> + hym8563: hym8563 at 51 { >> + compatible = "haoyu,hym8563"; >> + reg =<0x51>; >> + #clock-cells =<0>; >> + clock-frequency =<32768>; >> + clock-output-names = "xin32k"; >> + }; >> +}; >> \ No newline at end of file > missing newline as stated above Done. >> diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi >> new file mode 100644 >> index 0000000..b7459c0 >> --- /dev/null >> +++ b/arch/arm/boot/dts/rk3036.dtsi >> @@ -0,0 +1,381 @@ >> +/* >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This file is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This file is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include "skeleton.dtsi" > in general, please sort nodes by register address, so for example > > interrupt-controller at 10139000 > should be before > clock-controller at 20000000 > > same for all other nodes Done. >> + >> +/ { >> + compatible = "rockchip,rk3036"; >> + >> + interrupt-parent =<&gic>; >> + >> + aliases { >> + i2c1 =&i2c1; >> + serial0 =&uart0; >> + serial1 =&uart1; >> + serial2 =&uart2; >> + }; >> + >> + memory { >> + device_type = "memory"; >> + reg =<0x60000000 0x40000000>; > ordering is possible ... to ease readability I try to keep this as > > compatible = ... > reg = ... > [other properties sorted alphabetically] > status = ... Done. >> + }; >> + >> + arm-pmu { >> + compatible = "arm,cortex-a7-pmu"; >> + interrupts =, >> +; >> + interrupt-affinity =<&cpu0>,<&cpu1>; >> + }; > tabs, not spaces please Done. >> + >> + cpus { >> + #address-cells =<1>; >> + #size-cells =<0>; >> + enable-method = "rockchip,rk3036-smp"; > this enable method is not yet defined, please don't add it until actual smp is > accepted Done, removed it on this patch. >> + >> + cpu0: cpu at f00 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg =<0xf00>; >> + operating-points =< >> + /* KHz uV */ >> + 816000 1000000 >> + >; >> + #cooling-cells =<2>; /* min followed by max */ > again, not yet defined thermal handling, so the #cooling-cells should stay out > for now Done, removed it. >> + clock-latency =<40000>; >> + clocks =<&cru ARMCLK>; >> + resets =<&cru SRST_CORE0>; >> + }; >> + cpu1: cpu at f01 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg =<0xf01>; >> + resets =<&cru SRST_CORE1>; >> + }; >> + }; >> + >> + amba { >> + compatible = "arm,amba-bus"; >> + #address-cells =<1>; >> + #size-cells =<1>; >> + ranges; >> + >> + pdma: pdma at 20078000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg =<0x20078000 0x4000>; >> + interrupts =, >> +; >> + #dma-cells =<1>; >> + clocks =<&cru ACLK_DMAC2>; >> + clock-names = "apb_pclk"; >> + }; > again tabs please Done. >> + }; >> + >> + xin24m: oscillator { >> + compatible = "fixed-clock"; >> + clock-frequency =<24000000>; >> + clock-output-names = "xin24m"; >> + #clock-cells =<0>; >> + }; >> + >> + timer { >> + compatible = "arm,armv7-timer"; >> + arm,cpu-registers-not-fw-configured; >> + interrupts = IRQ_TYPE_LEVEL_HIGH)>, >> + , + > >> , + >> ; >> + clock-frequency =<24000000>; >> + }; >> + >> + cru: clock-controller at 20000000 { >> + compatible = "rockchip,rk3036-cru"; >> + reg =<0x20000000 0x1000>; >> + rockchip,grf =<&grf>; >> + #clock-cells =<1>; >> + #reset-cells =<1>; >> + assigned-clocks =<&cru PLL_GPLL>; >> + assigned-clock-rates =<594000000>; >> + }; >> + >> + uart0: serial at 20060000 { >> + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; >> + reg =<0x20060000 0x100>; >> + interrupts =; >> + reg-shift =<2>; >> + reg-io-width =<4>; >> + clock-frequency =<24000000>; >> + clocks =<&cru SCLK_UART0>,<&cru PCLK_UART0>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&uart0_xfer&uart0_cts&uart0_rts>; > status = "disabled" and then in the board.dts a > > &uart0 { > status = "okay"; > }; > > not everybody will want to use uart0 ... same is true for the other two uarts. Done. >> + }; >> + >> + uart1: serial at 20064000 { >> + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; >> + reg =<0x20064000 0x100>; >> + interrupts =; >> + reg-shift =<2>; >> + reg-io-width =<4>; >> + clock-frequency =<24000000>; >> + clocks =<&cru SCLK_UART1>,<&cru PCLK_UART1>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&uart1_xfer>; >> + }; >> + >> + uart2: serial at 20068000 { >> + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; >> + reg =<0x20068000 0x100>; >> + interrupts =; >> + reg-shift =<2>; >> + reg-io-width =<4>; >> + clock-frequency =<24000000>; >> + clocks =<&cru SCLK_UART2>,<&cru PCLK_UART2>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&uart2_xfer>; >> + }; >> + >> + pwm0: pwm at 20050000 { >> + compatible = "rockchip,rk2928-pwm"; > compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; > > rk2928-pwm matches now, but if we find issues we can simply create the rk3036- > pwm in the driver without needing to change the dts Done. >> + reg =<0x20050000 0x10>; >> + #pwm-cells =<3>; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&pwm0_pin>; >> + clocks =<&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + status = "disabled"; >> + }; >> + >> + pwm1: pwm at 20050010 { >> + compatible = "rockchip,rk2928-pwm"; >> + reg =<0x20050010 0x10>; >> + #pwm-cells =<3>; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&pwm1_pin>; >> + clocks =<&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + status = "disabled"; >> + }; >> + >> + pwm2: pwm at 20050020 { >> + compatible = "rockchip,rk2928-pwm"; >> + reg =<0x20050020 0x10>; >> + #pwm-cells =<3>; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&pwm2_pin>; >> + clocks =<&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + status = "disabled"; >> + }; >> + >> + pwm3: pwm at 20050030 { >> + compatible = "rockchip,rk2928-pwm"; >> + reg =<0x20050030 0x10>; >> + #pwm-cells =<2>; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&pwm3_pin>; >> + clocks =<&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + status = "disabled"; >> + }; >> + >> + sram: sram at 10080000 { >> + compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; >> + reg =<0x10080000 0x2000>; >> + }; >> + >> + gic: interrupt-controller at 10139000 { >> + compatible = "arm,gic-400"; >> + interrupt-controller; >> + #interrupt-cells =<3>; >> + #address-cells =<0>; >> + >> + reg =<0x10139000 0x1000>, >> + <0x1013a000 0x1000>, >> + <0x1013c000 0x2000>, >> + <0x1013e000 0x2000>; >> + interrupts =; >> + }; >> + >> + grf: syscon at 20008000 { >> + compatible = "rockchip,rk3036-grf", "syscon"; >> + reg =<0x20008000 0x1000>; >> + }; >> + >> + pinctrl: pinctrl { >> + compatible = "rockchip,rk3036-pinctrl"; >> + rockchip,grf =<&grf>; >> + #address-cells =<1>; >> + #size-cells =<1>; >> + ranges; >> + >> + gpio0: gpio0 at 2007c000 { >> + compatible = "rockchip,gpio-bank"; >> + reg =<0x2007c000 0x100>; >> + interrupts =; >> + clocks =<&cru PCLK_GPIO0>; >> + >> + gpio-controller; >> + #gpio-cells =<2>; >> + >> + interrupt-controller; >> + #interrupt-cells =<2>; >> + }; >> + >> + gpio1: gpio1 at 20080000 { >> + compatible = "rockchip,gpio-bank"; >> + reg =<0x20080000 0x100>; >> + interrupts =; >> + clocks =<&cru PCLK_GPIO1>; >> + >> + gpio-controller; >> + #gpio-cells =<2>; >> + >> + interrupt-controller; >> + #interrupt-cells =<2>; >> + }; >> + >> + gpio2: gpio2 at 20084000 { >> + compatible = "rockchip,gpio-bank"; >> + reg =<0x20084000 0x100>; >> + interrupts =; >> + clocks =<&cru PCLK_GPIO2>; >> + >> + gpio-controller; >> + #gpio-cells =<2>; >> + >> + interrupt-controller; >> + #interrupt-cells =<2>; >> + }; >> + >> + pcfg_pull_up: pcfg-pull-up { >> + bias-pull-up; >> + }; >> + >> + pcfg_pull_down: pcfg-pull-down { >> + bias-pull-down; >> + }; >> + >> + pcfg_pull_none: pcfg-pull-none { >> + bias-disable; >> + }; >> + >> + uart0 { >> + uart0_xfer: uart0-xfer { >> + rockchip,pins =<0 16 RK_FUNC_1&pcfg_pull_none>, > pcfg_pull_up for the rx-pin? Done >> + <0 17 RK_FUNC_1&pcfg_pull_none>; >> + }; >> + >> + uart0_cts: uart0-cts { >> + rockchip,pins =<0 18 RK_FUNC_1&pcfg_pull_none>; >> + }; > pcfg_pull_up again? > see ARM: dts: rockchip: pull up cts lines on rk3288 > (https://lkml.org/lkml/2015/9/2/612) for comparison Yes, they should be pull up. > >> + >> + uart0_rts: uart0-rts { >> + rockchip,pins =<0 19 RK_FUNC_1&pcfg_pull_none>; >> + }; >> + }; >> + >> + uart1 { >> + uart1_xfer: uart1-xfer { >> + rockchip,pins =<2 22 RK_FUNC_1&pcfg_pull_none>, >> + <2 23 RK_FUNC_1&pcfg_pull_none>; >> + }; >> + /* no rts / cts for uart1 */ >> + }; >> + >> + uart2 { >> + uart2_xfer: uart2-xfer { >> + rockchip,pins =<1 18 RK_FUNC_2 >> &pcfg_pull_none>, +<1 19 >> RK_FUNC_2&pcfg_pull_none>; + }; >> + /* no rts / cts for uart2 */ >> + }; > tabs please Sorry, done. >> + >> + pwm0 { >> + pwm0_pin: pwm0-pin { >> + rockchip,pins =<0 0 RK_FUNC_2&pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm1 { >> + pwm1_pin: pwm1-pin { >> + rockchip,pins =<0 1 RK_FUNC_2&pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm2 { >> + pwm2_pin: pwm2-pin { >> + rockchip,pins =<0 1 2&pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm3 { >> + pwm3_pin: pwm3-pin { >> + rockchip,pins =<0 27 1&pcfg_pull_none>; >> + }; >> + }; >> + >> + i2c1 { >> + i2c1_xfer: i2c1-xfer { >> + rockchip,pins =<0 2 RK_FUNC_1&pcfg_pull_none>, >> + <0 3 RK_FUNC_1&pcfg_pull_none>; >> + }; >> + }; >> + }; >> + >> + i2c1: i2c at 20056000 { >> + compatible = "rockchip,rk3288-i2c"; >> + reg =<0x20056000 0x1000>; >> + interrupts =; >> + #address-cells =<1>; >> + #size-cells =<0>; >> + clock-names = "i2c"; >> + clocks =<&cru PCLK_I2C1>; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&i2c1_xfer>; >> + status = "disabled"; >> + }; >> +}; > Thanks. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932347AbbIXCUj (ORCPT ); Wed, 23 Sep 2015 22:20:39 -0400 Received: from regular1.263xmail.com ([211.150.99.137]:57308 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755794AbbIXCUe (ORCPT ); Wed, 23 Sep 2015 22:20:34 -0400 X-263anti-spam: KSV:0;BIG:0;ABS:1;DNS:0;ATT:0;SPF:S; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ADDR-CHECKED: 0 X-RL-SENDER: zhengxing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhengxing@rock-chips.com X-UNIQUE-TAG: <63cca5496e88b4b1860ce19ad4625d71> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <56035D80.9080308@rock-chips.com> Date: Thu, 24 Sep 2015 10:18:40 +0800 From: Xing Zheng User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120410 Thunderbird/11.0.1 MIME-Version: 1.0 To: =?UTF-8?B?SGVpa28gU3TDvGJuZXI=?= CC: linux-rockchip@lists.infradead.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/9] ARM: dts: rockchip: add core rk3036 dts References: <1442478540-15068-1-git-send-email-zhengxing@rock-chips.com> <1442478540-15068-2-git-send-email-zhengxing@rock-chips.com> <3497055.MjziMiDfL7@diego> In-Reply-To: <3497055.MjziMiDfL7@diego> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2015年09月17日 17:18, Heiko Stübner wrote: > Am Donnerstag, 17. September 2015, 16:28:52 schrieb Xing Zheng: >> Initial release for rk3036, node definitions rk3036 sdk board. >> >> Signed-off-by: Xing Zheng >> --- >> >> Changes in v2: None >> >> arch/arm/boot/dts/Makefile | 1 + >> arch/arm/boot/dts/rk3036-sdk.dts | 62 +++++++ >> arch/arm/boot/dts/rk3036.dtsi | 381 >> ++++++++++++++++++++++++++++++++++++++ 3 files changed, 444 insertions(+) >> create mode 100644 arch/arm/boot/dts/rk3036-sdk.dts >> create mode 100644 arch/arm/boot/dts/rk3036.dtsi >> >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile >> index d39ce4b..48260c4 100644 >> --- a/arch/arm/boot/dts/Makefile >> +++ b/arch/arm/boot/dts/Makefile >> @@ -502,6 +502,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ >> rk3066a-bqcurie2.dtb \ >> rk3066a-marsboard.dtb \ >> rk3066a-rayeager.dtb \ >> + rk3036-sdk.dtb \ > ordering ... please put the rk3036 above rk3066 boards Done. > >> rk3188-radxarock.dtb \ >> rk3288-evb-act8846.dtb \ >> rk3288-evb-rk808.dtb \ >> diff --git a/arch/arm/boot/dts/rk3036-sdk.dts >> b/arch/arm/boot/dts/rk3036-sdk.dts new file mode 100644 >> index 0000000..9187f93 >> --- /dev/null >> +++ b/arch/arm/boot/dts/rk3036-sdk.dts > or "rk3036-evb.dts"? What is the actual board named? Done, use rk3036-evb.dts >> @@ -0,0 +1,62 @@ >> +/* >> + * Copyright (c) 2015 Xing Zheng > this probably wants a Rockchip copyright notice? Yes, remove this notice. >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This file is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This file is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +/dts-v1/; >> + >> +#include "rk3036.dtsi" >> + >> +/ { >> + model = "SDK-RK3036"; >> + compatible = "sdk,sdk-rk3036", "rockchip,rk3036"; > model = "Rockchip RK3036-SDK"; > compatible = "rockchip,rk3036-sdk", "rockchip,rk3036"; > > or > > model = "Rockchip RK3036 Evaluation board"; > compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; > > depending on what the real board is labeled Done. >> +}; >> + >> +&i2c1 { >> + status = "okay"; >> + >> + hym8563: hym8563@51 { >> + compatible = "haoyu,hym8563"; >> + reg =<0x51>; >> + #clock-cells =<0>; >> + clock-frequency =<32768>; >> + clock-output-names = "xin32k"; >> + }; >> +}; >> \ No newline at end of file > missing newline as stated above Done. >> diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi >> new file mode 100644 >> index 0000000..b7459c0 >> --- /dev/null >> +++ b/arch/arm/boot/dts/rk3036.dtsi >> @@ -0,0 +1,381 @@ >> +/* >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This file is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This file is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include "skeleton.dtsi" > in general, please sort nodes by register address, so for example > > interrupt-controller@10139000 > should be before > clock-controller@20000000 > > same for all other nodes Done. >> + >> +/ { >> + compatible = "rockchip,rk3036"; >> + >> + interrupt-parent =<&gic>; >> + >> + aliases { >> + i2c1 =&i2c1; >> + serial0 =&uart0; >> + serial1 =&uart1; >> + serial2 =&uart2; >> + }; >> + >> + memory { >> + device_type = "memory"; >> + reg =<0x60000000 0x40000000>; > ordering is possible ... to ease readability I try to keep this as > > compatible = ... > reg = ... > [other properties sorted alphabetically] > status = ... Done. >> + }; >> + >> + arm-pmu { >> + compatible = "arm,cortex-a7-pmu"; >> + interrupts =, >> +; >> + interrupt-affinity =<&cpu0>,<&cpu1>; >> + }; > tabs, not spaces please Done. >> + >> + cpus { >> + #address-cells =<1>; >> + #size-cells =<0>; >> + enable-method = "rockchip,rk3036-smp"; > this enable method is not yet defined, please don't add it until actual smp is > accepted Done, removed it on this patch. >> + >> + cpu0: cpu@f00 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg =<0xf00>; >> + operating-points =< >> + /* KHz uV */ >> + 816000 1000000 >> + >; >> + #cooling-cells =<2>; /* min followed by max */ > again, not yet defined thermal handling, so the #cooling-cells should stay out > for now Done, removed it. >> + clock-latency =<40000>; >> + clocks =<&cru ARMCLK>; >> + resets =<&cru SRST_CORE0>; >> + }; >> + cpu1: cpu@f01 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg =<0xf01>; >> + resets =<&cru SRST_CORE1>; >> + }; >> + }; >> + >> + amba { >> + compatible = "arm,amba-bus"; >> + #address-cells =<1>; >> + #size-cells =<1>; >> + ranges; >> + >> + pdma: pdma@20078000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg =<0x20078000 0x4000>; >> + interrupts =, >> +; >> + #dma-cells =<1>; >> + clocks =<&cru ACLK_DMAC2>; >> + clock-names = "apb_pclk"; >> + }; > again tabs please Done. >> + }; >> + >> + xin24m: oscillator { >> + compatible = "fixed-clock"; >> + clock-frequency =<24000000>; >> + clock-output-names = "xin24m"; >> + #clock-cells =<0>; >> + }; >> + >> + timer { >> + compatible = "arm,armv7-timer"; >> + arm,cpu-registers-not-fw-configured; >> + interrupts = IRQ_TYPE_LEVEL_HIGH)>, >> + , + > >> , + >> ; >> + clock-frequency =<24000000>; >> + }; >> + >> + cru: clock-controller@20000000 { >> + compatible = "rockchip,rk3036-cru"; >> + reg =<0x20000000 0x1000>; >> + rockchip,grf =<&grf>; >> + #clock-cells =<1>; >> + #reset-cells =<1>; >> + assigned-clocks =<&cru PLL_GPLL>; >> + assigned-clock-rates =<594000000>; >> + }; >> + >> + uart0: serial@20060000 { >> + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; >> + reg =<0x20060000 0x100>; >> + interrupts =; >> + reg-shift =<2>; >> + reg-io-width =<4>; >> + clock-frequency =<24000000>; >> + clocks =<&cru SCLK_UART0>,<&cru PCLK_UART0>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&uart0_xfer&uart0_cts&uart0_rts>; > status = "disabled" and then in the board.dts a > > &uart0 { > status = "okay"; > }; > > not everybody will want to use uart0 ... same is true for the other two uarts. Done. >> + }; >> + >> + uart1: serial@20064000 { >> + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; >> + reg =<0x20064000 0x100>; >> + interrupts =; >> + reg-shift =<2>; >> + reg-io-width =<4>; >> + clock-frequency =<24000000>; >> + clocks =<&cru SCLK_UART1>,<&cru PCLK_UART1>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&uart1_xfer>; >> + }; >> + >> + uart2: serial@20068000 { >> + compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; >> + reg =<0x20068000 0x100>; >> + interrupts =; >> + reg-shift =<2>; >> + reg-io-width =<4>; >> + clock-frequency =<24000000>; >> + clocks =<&cru SCLK_UART2>,<&cru PCLK_UART2>; >> + clock-names = "baudclk", "apb_pclk"; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&uart2_xfer>; >> + }; >> + >> + pwm0: pwm@20050000 { >> + compatible = "rockchip,rk2928-pwm"; > compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; > > rk2928-pwm matches now, but if we find issues we can simply create the rk3036- > pwm in the driver without needing to change the dts Done. >> + reg =<0x20050000 0x10>; >> + #pwm-cells =<3>; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&pwm0_pin>; >> + clocks =<&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + status = "disabled"; >> + }; >> + >> + pwm1: pwm@20050010 { >> + compatible = "rockchip,rk2928-pwm"; >> + reg =<0x20050010 0x10>; >> + #pwm-cells =<3>; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&pwm1_pin>; >> + clocks =<&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + status = "disabled"; >> + }; >> + >> + pwm2: pwm@20050020 { >> + compatible = "rockchip,rk2928-pwm"; >> + reg =<0x20050020 0x10>; >> + #pwm-cells =<3>; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&pwm2_pin>; >> + clocks =<&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + status = "disabled"; >> + }; >> + >> + pwm3: pwm@20050030 { >> + compatible = "rockchip,rk2928-pwm"; >> + reg =<0x20050030 0x10>; >> + #pwm-cells =<2>; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&pwm3_pin>; >> + clocks =<&cru PCLK_PWM>; >> + clock-names = "pwm"; >> + status = "disabled"; >> + }; >> + >> + sram: sram@10080000 { >> + compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; >> + reg =<0x10080000 0x2000>; >> + }; >> + >> + gic: interrupt-controller@10139000 { >> + compatible = "arm,gic-400"; >> + interrupt-controller; >> + #interrupt-cells =<3>; >> + #address-cells =<0>; >> + >> + reg =<0x10139000 0x1000>, >> + <0x1013a000 0x1000>, >> + <0x1013c000 0x2000>, >> + <0x1013e000 0x2000>; >> + interrupts =; >> + }; >> + >> + grf: syscon@20008000 { >> + compatible = "rockchip,rk3036-grf", "syscon"; >> + reg =<0x20008000 0x1000>; >> + }; >> + >> + pinctrl: pinctrl { >> + compatible = "rockchip,rk3036-pinctrl"; >> + rockchip,grf =<&grf>; >> + #address-cells =<1>; >> + #size-cells =<1>; >> + ranges; >> + >> + gpio0: gpio0@2007c000 { >> + compatible = "rockchip,gpio-bank"; >> + reg =<0x2007c000 0x100>; >> + interrupts =; >> + clocks =<&cru PCLK_GPIO0>; >> + >> + gpio-controller; >> + #gpio-cells =<2>; >> + >> + interrupt-controller; >> + #interrupt-cells =<2>; >> + }; >> + >> + gpio1: gpio1@20080000 { >> + compatible = "rockchip,gpio-bank"; >> + reg =<0x20080000 0x100>; >> + interrupts =; >> + clocks =<&cru PCLK_GPIO1>; >> + >> + gpio-controller; >> + #gpio-cells =<2>; >> + >> + interrupt-controller; >> + #interrupt-cells =<2>; >> + }; >> + >> + gpio2: gpio2@20084000 { >> + compatible = "rockchip,gpio-bank"; >> + reg =<0x20084000 0x100>; >> + interrupts =; >> + clocks =<&cru PCLK_GPIO2>; >> + >> + gpio-controller; >> + #gpio-cells =<2>; >> + >> + interrupt-controller; >> + #interrupt-cells =<2>; >> + }; >> + >> + pcfg_pull_up: pcfg-pull-up { >> + bias-pull-up; >> + }; >> + >> + pcfg_pull_down: pcfg-pull-down { >> + bias-pull-down; >> + }; >> + >> + pcfg_pull_none: pcfg-pull-none { >> + bias-disable; >> + }; >> + >> + uart0 { >> + uart0_xfer: uart0-xfer { >> + rockchip,pins =<0 16 RK_FUNC_1&pcfg_pull_none>, > pcfg_pull_up for the rx-pin? Done >> + <0 17 RK_FUNC_1&pcfg_pull_none>; >> + }; >> + >> + uart0_cts: uart0-cts { >> + rockchip,pins =<0 18 RK_FUNC_1&pcfg_pull_none>; >> + }; > pcfg_pull_up again? > see ARM: dts: rockchip: pull up cts lines on rk3288 > (https://lkml.org/lkml/2015/9/2/612) for comparison Yes, they should be pull up. > >> + >> + uart0_rts: uart0-rts { >> + rockchip,pins =<0 19 RK_FUNC_1&pcfg_pull_none>; >> + }; >> + }; >> + >> + uart1 { >> + uart1_xfer: uart1-xfer { >> + rockchip,pins =<2 22 RK_FUNC_1&pcfg_pull_none>, >> + <2 23 RK_FUNC_1&pcfg_pull_none>; >> + }; >> + /* no rts / cts for uart1 */ >> + }; >> + >> + uart2 { >> + uart2_xfer: uart2-xfer { >> + rockchip,pins =<1 18 RK_FUNC_2 >> &pcfg_pull_none>, +<1 19 >> RK_FUNC_2&pcfg_pull_none>; + }; >> + /* no rts / cts for uart2 */ >> + }; > tabs please Sorry, done. >> + >> + pwm0 { >> + pwm0_pin: pwm0-pin { >> + rockchip,pins =<0 0 RK_FUNC_2&pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm1 { >> + pwm1_pin: pwm1-pin { >> + rockchip,pins =<0 1 RK_FUNC_2&pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm2 { >> + pwm2_pin: pwm2-pin { >> + rockchip,pins =<0 1 2&pcfg_pull_none>; >> + }; >> + }; >> + >> + pwm3 { >> + pwm3_pin: pwm3-pin { >> + rockchip,pins =<0 27 1&pcfg_pull_none>; >> + }; >> + }; >> + >> + i2c1 { >> + i2c1_xfer: i2c1-xfer { >> + rockchip,pins =<0 2 RK_FUNC_1&pcfg_pull_none>, >> + <0 3 RK_FUNC_1&pcfg_pull_none>; >> + }; >> + }; >> + }; >> + >> + i2c1: i2c@20056000 { >> + compatible = "rockchip,rk3288-i2c"; >> + reg =<0x20056000 0x1000>; >> + interrupts =; >> + #address-cells =<1>; >> + #size-cells =<0>; >> + clock-names = "i2c"; >> + clocks =<&cru PCLK_I2C1>; >> + pinctrl-names = "default"; >> + pinctrl-0 =<&i2c1_xfer>; >> + status = "disabled"; >> + }; >> +}; > Thanks.