Re: [meta-fsl-arm PATCH 1/3] u-boot-fslc: Update to 2015.10-based fork

[Bob Cochran <yocto@mindchasers.com>]

On 09/24/2015 01:39 PM, Otavio Salvador wrote:
> On Thu, Sep 24, 2015 at 2:36 PM, Bob Cochran <yocto@mindchasers.com> wrote:
>> On 09/24/2015 01:03 PM, Otavio Salvador wrote:
>>>
>>> This updates the fork based on upcoming 2015.10 release. This is
>>> currently based on 2015.10-rc3 tag and offers a very solid release for
>>> start the tests for Yocto Project 2.0 release.
>>
>> Is u-boot-fslc intended to support qoriq arm boards?   Are you or others
>> testing with it against qoriq arm parts, or should we stick with
>> u-boot_qoriq for an LS1A part?
>
> It does  support it but I never tested it. If you are willing to get
> it working and send the patches I would love to get it merged ;-)
>

Thanks. I'm impressed that 2015.10 u-boot, which I built using 
u-boot-fslc_2015.10.bb, booted on the first try with my brand new Rev 
2.0 silicon TWR-LS1021A-PB.

I took your recipe patch and applied it to the meta-freescale 
github-based layer and built it using poky master.   All I had to do was 
add qoriq as a compatible machine and change the preferred provider in a 
conf file.

I wasn't as lucky with Linux.  It did hang far into the boot process 
while booting FSL's SDK kernel built using the SDK toolchain.

I started comparing the u-boot git logs for ls1021a related commits 
between the mainline repo and the fsl qoriq repo.  I wasn't surprised 
that some might be missing in the mainline, which maybe is the root 
cause of Linux hanging during boot.

You can count me in to help with this as we move along.  I'll reply 
again in a few days after I dig in further.


A screen shot is provided below of u-boot booting.  Also, a snippet of 
where Linux hangs is also provided below.  I'll appreciate any guidance 
on where to look for why it's hanging.



U-Boot 2015.10-rc3+fslc+gf4cd146 (Sep 24 2015 - 16:23:55 -0400)

CPU:   Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)
Clock Configuration:
        CPU0(ARMV7):1000 MHz,
        Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate),
Reset Configuration Word (RCW):
        00000000: 0608000a 00000000 00000000 00000000
        00000010: 70000000 00007900 e0025a00 21046000
        00000020: 00000000 00000000 00000000 20000000
        00000030: 00080000 881b7340 00000000 00000000
Board: LS1021ATWR
CPLD:  V2.0
PCBA:  V1.0
VBank: 1
I2C:   ready
DRAM:  1 GiB
Using SERDES1 Protocol: 112 (0x70)
Not a microcode
Flash: 128 MiB
MMC:   FSL_SDHC: 0
EEPROM: NXID v16777216
PCIe1: Root Complex no link, regs @ 0x3400000
PCIe2: Root Complex no link, regs @ 0x3500000
In:    serial
Out:   serial
Err:   serial
SEC: RNG instantiated
Net:   eTSEC2 is in sgmii mode.
eTSEC1, eTSEC2, eTSEC3 [PRIME]
Hit any key to stop autoboot:  0






....
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
Key type dns_resolver registered
regulator-dummy: disabling
hub 1-1:1.0: USB hub found
drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
hub 1-1:1.0: 4 ports detected
usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
usb 2-1: Parent hub missing LPM exit latency info.  Power management 
will be impacted.
hub 2-1:1.0: USB hub found
hub 2-1:1.0: 4 ports detected
libphy: mdio@2d24000:01 - Link is Up - 1000/Full
IP-Config: Gateway not on directly connected network
ALSA device list:
   #0: FSL-VF610-TWR-BOARD