From: John David Anglin <dave.anglin@bell.net>
To: James Bottomley <James.Bottomley@HansenPartnership.com>
Cc: Helge Deller <deller@gmx.de>, linux-parisc@vger.kernel.org
Subject: Re: [PATCH] parisc: adjust L1_CACHE_BYTES to 128 bytes on PA8800 and PA8900 CPUs
Date: Fri, 25 Sep 2015 11:56:25 -0400 [thread overview]
Message-ID: <56056EA9.9070404@bell.net> (raw)
In-Reply-To: <BA678D0F-591B-4925-A50B-852C0C3419F7@bell.net>
On 2015-09-25 8:20 AM, John David Anglin wrote:
> Our atomic_t types are guarded by ldcw locks. So, they are not really subject to contention.
> You could be correct that L1_CACHE_BYTES could be reduced to 16 (i.e., maximum alignment
> needed for any type on parisc) provided it isn't used somewhere where we need the actual L1
> cache line size as returned by the PDC.
Digging through various documentation, I now believe that L1_CACHE_BYTES
is 16 bytes on ALL PA-RISC
processors. We are getting confused by the L2 length reported by the
PDC. The PA-8800 is essentially
two PA-8700s integrated on the same die.
See page 10 in this document:
https://parisc.wiki.kernel.org/images-parisc/e/e9/PA-8700wp.pdf
It shows the PA-8700 L1 design.
Dave
--
John David Anglin dave.anglin@bell.net
next prev parent reply other threads:[~2015-09-25 15:56 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-02 16:20 [PATCH] parisc: adjust L1_CACHE_BYTES to 128 bytes on PA8800 and PA8900 CPUs Helge Deller
2015-09-03 13:30 ` James Bottomley
2015-09-03 13:57 ` James Bottomley
2015-09-05 21:30 ` Helge Deller
2015-09-22 16:20 ` Helge Deller
2015-09-23 0:12 ` John David Anglin
2015-09-23 19:30 ` Helge Deller
2015-09-23 21:00 ` John David Anglin
2015-09-24 14:20 ` James Bottomley
2015-09-24 16:39 ` John David Anglin
2015-09-24 16:57 ` James Bottomley
2015-09-25 12:20 ` John David Anglin
2015-09-25 15:56 ` John David Anglin [this message]
2015-09-27 16:27 ` [PATCH] parisc: " John David Anglin
2015-09-28 15:57 ` Helge Deller
2015-09-28 20:00 ` John David Anglin
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