Re: [PATCH v2 5/7] drm/i915/dp_mst: Track DSC enabled status on the MST link

["Hogander, Jouni" <jouni.hogander@intel.com>]

On Wed, 2025-10-15 at 19:19 +0300, Imre Deak wrote:
> Track whether DSC is enabled on any CRTC on a link. On DP-SST (and
> DSI)
> this will always match the CRTC's DSC state, those links having only
> a
> single stream (aka CRTC). For instance, on DP-MST if DSC is enabled
> for
> CRTC#0, but disabled for CRTC#1, the DSC/FEC state for these CRTCs
> will
> be as follows:
> 
> CRTC#0:
>  - compression_enable = true
>  - compression_enabled_on_link = true
>  - fec_enable = true for 8b10b, false for 128b132b
> 
> CRTC#1:
>  - compression_enable = false
>  - compression_enabled_on_link = true
>  - fec_enable = true for 8b10b, false for 128b132b
> 
> This patch only sets compression_enabled_on_link for CRTC#0 above and
> enables FEC on CRTC#0 if DSC was enabled on any other CRTC on the
> 8b10b
> MST link. A follow-up change will make sure that the state of all the
> CRTCs (CRTC#1 above) on an MST link is recomputed if DSC gets enabled
> on
> any CRTC, setting compression_enabled_on_link and fec_enable for
> these.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h |  2 ++
>  drivers/gpu/drm/i915/display/intel_dp.c            |  2 +-
>  drivers/gpu/drm/i915/display/intel_vdsc.c          | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_vdsc.h          |  1 +
>  4 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 87b7cec35320f..58308146697ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1277,6 +1277,8 @@ struct intel_crtc_state {
>  
>  	/* Display Stream compression state */
>  	struct {
> +		/* Only used for state computation, not read out
> from the HW. */
> +		bool compression_enabled_on_link;
>  		bool compression_enable;
>  		int num_streams;
>  		/* Compressed Bpp in U6.4 format (first 4 bits for
> fractional part) */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3ffb015004c54..8ba931204cb52 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2387,7 +2387,7 @@ bool intel_dp_needs_8b10b_fec(const struct
> intel_crtc_state *crtc_state,
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>  		return false;
>  
> -	return dsc_enabled_on_crtc;
> +	return dsc_enabled_on_crtc ||
> intel_dsc_enabled_on_link(crtc_state);
>  }
>  
>  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 64a1e9f0a1893..316753205ac45 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -374,9 +374,20 @@ int intel_dsc_compute_params(struct
> intel_crtc_state *pipe_config)
>  
>  void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state)
>  {
> +	crtc_state->dsc.compression_enabled_on_link = true;
>  	crtc_state->dsc.compression_enable = true;
>  }
>  
> +bool intel_dsc_enabled_on_link(const struct intel_crtc_state
> *crtc_state)
> +{
> +	struct intel_display *display =
> to_intel_display(crtc_state);
> +
> +	drm_WARN_ON(display->drm, crtc_state->dsc.compression_enable
> &&
> +		    !crtc_state->dsc.compression_enabled_on_link);
> +
> +	return crtc_state->dsc.compression_enabled_on_link;
> +}
> +
>  enum intel_display_power_domain
>  intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder
> cpu_transcoder)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h
> b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 240bef82d3576..9c52ece0027c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -21,6 +21,7 @@ void intel_dsc_enable(const struct intel_crtc_state
> *crtc_state);
>  void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
>  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
>  void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state);
> +bool intel_dsc_enabled_on_link(const struct intel_crtc_state
> *crtc_state);
>  void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
>  enum intel_display_power_domain
>  intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder
> cpu_transcoder);