From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush
Date: Mon, 28 Sep 2015 17:35:22 +0100 [thread overview]
Message-ID: <56096C4A.5090007@linux.intel.com> (raw)
In-Reply-To: <20150928160223.GR26517@intel.com>
On 28/09/2015 17:02, Ville Syrjälä wrote:
> On Mon, Sep 28, 2015 at 04:51:52PM +0100, Arun Siluvery wrote:
>> On 25/09/2015 18:09, Ville Syrjälä wrote:
>>> On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote:
>>>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>>>> 1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>>> index ab5ac5e..093a5e4 100644
>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>> @@ -63,6 +63,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>>>> /* WaDisableKillLogic:bxt,skl */
>>>> I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>>>> ECOCHK_DIS_TLB);
>>>> +
>>>> + /* WaOCLCoherentLineFlush:skl,bxt */
>>>> + I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>>>> + GEN8_LQSC_FLUSH_COHERENT_LINES));
>>>
>>> According to Bspec + w/a db this should be done for BDW too (actually
>>> BSpec shows it for BDW only?). If that's the case, then we should be
>>> able to kill gen8_emit_flush_coherentl3_wa(), no? Well, as long as
>>> someone goes and adds the DC flush to the normal post batch flush.
>>>
>> Yes this is applicable for BDW also but I wanted to keep only Gen9
>> patches in this series. I will send separate patch for BDW.
>> We would still need gen8_emit_flush_coherentl3_wa() because WA requires
>> that the flush need to happen from the WA batch itself during context
>> switch.
>
> If we already flush all coherent lines out from DC after each batch,
> how can there still be coherent lines in the DC on a context switch?
>
> But spelling that out made me think that mid-batch preemption would
> still need it I suppose. But w/o preemption I see no reason why it
> would be needed.
>
Yes, this is to account preemption case (sorry I should've mentioned
earlier). Most of the workarounds in WA batch are to account for
preemption related issues.
regards
Arun
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-09-28 16:35 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-25 13:33 [PATCH 00/12] Gen9: Changes to add/merge/update/remove WA Arun Siluvery
2015-09-25 13:33 ` [PATCH 01/12] drm/i915/gen9: Handle error returned by gen9_init_workarounds Arun Siluvery
2015-09-25 17:47 ` Ville Syrjälä
2015-09-28 13:55 ` Daniel Vetter
2015-09-25 13:33 ` [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush Arun Siluvery
2015-09-25 17:09 ` Ville Syrjälä
2015-09-28 15:51 ` Arun Siluvery
2015-09-28 16:02 ` Ville Syrjälä
2015-09-28 16:35 ` Arun Siluvery [this message]
2015-09-25 13:33 ` [PATCH 03/12] drm/i915/gen9: Merge two WA as they part of same register Arun Siluvery
2015-09-25 17:47 ` Ville Syrjälä
2015-09-28 13:56 ` Daniel Vetter
2015-09-25 13:33 ` [PATCH 04/12] drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA Arun Siluvery
2015-09-25 17:12 ` Ville Syrjälä
2015-09-28 8:47 ` Jani Nikula
2015-09-28 13:56 ` Daniel Vetter
2015-09-25 13:33 ` [PATCH 05/12] drm/i915/bxt: update WaSetHDCunitClckGatingDisable Arun Siluvery
2015-09-25 17:32 ` Ville Syrjälä
2015-09-25 13:33 ` [PATCH 06/12] drm/i915/bxt: Add WaStoreMultiplePTEenable name Arun Siluvery
2015-09-25 17:34 ` Ville Syrjälä
2015-09-28 13:57 ` Daniel Vetter
2015-09-25 13:33 ` [PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating Arun Siluvery
2015-09-25 17:17 ` Ville Syrjälä
2015-09-28 11:06 ` Imre Deak
2015-09-28 11:09 ` Arun Siluvery
2015-09-25 13:33 ` [PATCH 08/12] drm/i915/skl: Remove WaDisableSDEUnitClockGating Arun Siluvery
2015-09-25 17:39 ` Ville Syrjälä
2015-09-28 13:58 ` Daniel Vetter
2015-09-25 13:33 ` [PATCH 09/12] drm/i915/skl: Remove WaSetGAPSunitClckGateDisable Arun Siluvery
2015-09-25 17:43 ` Ville Syrjälä
2015-09-25 13:33 ` [PATCH 10/12] drm/i915/skl: Remove WaDisableVFUnitClockGating Arun Siluvery
2015-09-25 17:45 ` Ville Syrjälä
2015-09-28 14:01 ` Daniel Vetter
2015-09-25 13:33 ` [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken Arun Siluvery
2015-09-25 18:34 ` Ville Syrjälä
2015-09-25 18:43 ` Ville Syrjälä
2015-09-25 21:39 ` Arun Siluvery
2015-09-25 13:33 ` [PATCH 12/12] drm/i915:skl: Remove WaDisablePowerCompilerClockGating Arun Siluvery
2015-09-25 17:24 ` Ville Syrjälä
2015-09-28 11:21 ` [PATCH 00/12] Gen9: Changes to add/merge/update/remove WA Arun Siluvery
2015-09-28 14:03 ` Daniel Vetter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=56096C4A.5090007@linux.intel.com \
--to=arun.siluvery@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=mika.kuoppala@intel.com \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.