From mboxrd@z Thu Jan 1 00:00:00 1970 References: <55E5F849.1070708@xenomai.org> <55E5FB89.3080604@xenomai.org> <55E60743.30600@xenomai.org> <5604517A.2000602@mperpetuo.com> <20150925150248.GE1332@hermes.click-hack.org> <560580E6.6070208@mperpetuo.com> <20150925180137.GF1332@hermes.click-hack.org> <20150926112419.GH1332@hermes.click-hack.org> <20150929001233.GB15767@hermes.click-hack.org> <560A89FC.9060808@xenomai.org> From: Dmitriy Cherkasov Message-ID: <560ACAF1.2020305@mperpetuo.com> Date: Tue, 29 Sep 2015 10:31:29 -0700 MIME-Version: 1.0 In-Reply-To: <560A89FC.9060808@xenomai.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Xenomai] xenomai/ipipe arm64 port List-Id: Discussions about the Xenomai project List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: xenomai@xenomai.org On 09/29/2015 05:54 AM, Jorge Ramirez Ortiz wrote: > On 09/28/2015 08:12 PM, Gilles Chanteperdrix wrote: >> On Mon, Sep 28, 2015 at 04:57:28PM -0700, Dmitriy Cherkasov wrote: >> Ok, this page: >> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CJHECGIH.html >> >> seems to indicate that armv8 may or may not trap upon >> exception. Or maybe the exceptions can be enabled with the FPCR >> register? Or the glibc functions defined in the fenv.h header? >> > the way it is worded it appears to be a decision left to the SoC vendor. > I'll post the question to support@arm.com for confirmation. > From some earlier docs, it looks like it was possible to toggle trapping with FPCR, but as Lennart mentioned those bits appear to now be reserved. On our hardware, setting them has no effect. I also enjoyed this part: Both floating-point and NEON are required in all standard ARMv8 implementations. However, implementations targeting specialized markets may support the following combinations: * No NEON or floating-point