Re: [Xenomai] xenomai/ipipe arm64 port

[Jorge Ramirez Ortiz <jro@xenomai.org>]

On 09/29/2015 01:47 PM, Gilles Chanteperdrix wrote:
> On Tue, Sep 29, 2015 at 10:31:29AM -0700, Dmitriy Cherkasov wrote:
>>
>>
>> On 09/29/2015 05:54 AM, Jorge Ramirez Ortiz wrote:
>>> On 09/28/2015 08:12 PM, Gilles Chanteperdrix wrote:
>>>> On Mon, Sep 28, 2015 at 04:57:28PM -0700, Dmitriy Cherkasov wrote:
>>>> Ok, this page:
>>>> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CJHECGIH.html
>>>>
>>>> seems to indicate that armv8 may or may not trap upon
>>>> exception. Or maybe the exceptions can be enabled with the FPCR
>>>> register? Or the glibc functions defined in the fenv.h header?
>>>>
>>> the way it is worded it appears to be a decision left to the SoC vendor.
>>> I'll post the question to support@arm.com for confirmation.
>>>
>>  From some earlier docs, it looks like it was possible to toggle 
>> trapping with FPCR, but as Lennart mentioned those bits appear to now be 
>> reserved. On our hardware, setting them has no effect.
>>
>>
>> I also enjoyed this part:
>>
>> Both floating-point and NEON are required in all standard ARMv8 
>> implementations. However, implementations targeting specialized markets 
>> may support the following combinations:
>>
>>   *
>>
>>     No NEON or floating-point
> 
> Well, I guess there is a difference between "standard" and
> "implementation targeting specialized markets".
> 

the answer from ARM with respect to exception trapping and FPU :

"Only if the SoC vendor has an ARM architectural license and it was one of their
custom processors, FPU and exception trapping might or might not be present.
All current ARMv8-A processors designed by ARM support floating-point and SIMD
support without exception trapping. "



-- 
jro