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Subject: Re: [PATCH] mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600
To: Brian Norris <computersforpeace@gmail.com>
References: <1441187581-12928-1-git-send-email-sr@denx.de>
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Cc: linux-mtd@lists.infradead.org, Linus Walleij <linus.walleij@linaro.org>,
 Viresh Kumar <viresh.kumar@linaro.org>,
 Boris Brezillon <boris.brezillon@free-electrons.com>
From: Stefan Roese <sr@denx.de>
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Date: Fri, 2 Oct 2015 12:33:58 +0200
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Hi Brian,

On 29.09.2015 02:21, Brian Norris wrote:
> On Wed, Sep 02, 2015 at 11:53:01AM +0200, Stefan Roese wrote:
>> This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
>> be used by boards equipped with a NAND chip that requires 4-bit ECC
>> strength. The SPEAr600 HW ECC only supports 1-bit ECC strength.
>>
>> To enable SW BCH4, you need to specify this in your nand controller
>> DT node:
>>
>> 	nand-ecc-mode = "soft_bch";
>
> Please update the DT binding file, referring to nand.txt. Just specify
> your additional restrictions (like, should be "soft_bch" or "hw").
>
> Also please use nand-ecc-strength and nand-ecc-size; see below.

Thanks for the review. I'll send a new patch (series) out shortly,
addressing all your comments and suggestions.

Thanks,
Stefan