From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52339) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhxiH-0004ak-TH for qemu-devel@nongnu.org; Fri, 02 Oct 2015 06:37:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZhxiC-0004WF-R5 for qemu-devel@nongnu.org; Fri, 02 Oct 2015 06:37:17 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:61175) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhxiC-0004W9-LG for qemu-devel@nongnu.org; Fri, 02 Oct 2015 06:37:12 -0400 References: <1436163304-6167-1-git-send-email-serge.vakulenko@gmail.com> <1436163304-6167-5-git-send-email-serge.vakulenko@gmail.com> From: Leon Alrae Message-ID: <560E5E50.6060005@imgtec.com> Date: Fri, 2 Oct 2015 11:37:04 +0100 MIME-Version: 1.0 In-Reply-To: <1436163304-6167-5-git-send-email-serge.vakulenko@gmail.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH pic32 v3 04/16] pic32: add two MIPS processor variants: M4K and microAptivUP List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Serge Vakulenko , qemu-devel@nongnu.org Cc: Aurelien Jarno Hi Serge, On 06/07/15 07:14, Serge Vakulenko wrote: > Needed for pic32mx (M4K) and pic32mz (microAptivUP) simulation. > > Signed-off-by: Serge Vakulenko > --- > target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) This patch looks good, but these new cores have VEIC support enabled so I think it should go together with patch #3 which actually implements EIC. These patches don't need to wait until entire series is ready, thus if you address Aurelien's comment related to introducing CP0Ca_RIPL_mask in patch #3, then I could cherry-pick these two patches and apply to target-mips queue. Thanks, Leon