From mboxrd@z Thu Jan 1 00:00:00 1970 From: sergei.shtylyov@cogentembedded.com (Sergei Shtylyov) Date: Fri, 2 Oct 2015 17:32:10 +0300 Subject: [PATCH] ARM: debug: add support for alternate 8250 register layout In-Reply-To: References: <1443787929-19173-1-git-send-email-mans@mansr.com> <560E9268.60900@cogentembedded.com> Message-ID: <560E956A.6070700@cogentembedded.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 10/2/2015 5:26 PM, M?ns Rullg?rd wrote: >>> Some SoCs have a UART with a non-standard register layout. This >>> allows the debug console to work with these. >> >>> Signed-off-by: Mans Rullgard >>> --- >>> I would have preferred a more accurate description of the UART, but I've >>> not managed to figure out who the vendor is. >> >> You haven't seem the Alchemy datasheets? I can send you some if so. > > I have. They don't say where Alchemy bought the UART block. In fact, seeing at least Au1550 databook googling for "alchemy databook". The UART registers are described there. Perhaps, it's not accurate enought for your needs, though... >>> --- >>> arch/arm/Kconfig.debug | 4 ++++ >>> arch/arm/include/debug/8250.S | 12 ++++++++++++ >>> 2 files changed, 16 insertions(+) >>> >>> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug >>> index 0cfd7f9..8d5c837 100644 >>> --- a/arch/arm/Kconfig.debug >>> +++ b/arch/arm/Kconfig.debug >>> @@ -1597,6 +1597,10 @@ config DEBUG_UART_8250_WORD >>> DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \ >>> DEBUG_BRCMSTB_UART >>> >>> +config DEBUG_UART_8250_AU >>> + bool "8250 UART has Alchemy register layout" >>> + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 >>> + >> >> So Alchemy UART got reused on ARM? > > The UART is actually a Palmchip IP core used by several SoC companies. Hm, how have you figured out that;s Palmchip if the Alchemy databooks are silent about that? :-) MBR, Sergei From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752442AbbJBOcO (ORCPT ); Fri, 2 Oct 2015 10:32:14 -0400 Received: from mail-la0-f41.google.com ([209.85.215.41]:34361 "EHLO mail-la0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751800AbbJBOcN (ORCPT ); Fri, 2 Oct 2015 10:32:13 -0400 Subject: Re: [PATCH] ARM: debug: add support for alternate 8250 register layout To: =?UTF-8?B?TcOlbnMgUnVsbGfDpXJk?= References: <1443787929-19173-1-git-send-email-mans@mansr.com> <560E9268.60900@cogentembedded.com> Cc: Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org From: Sergei Shtylyov Message-ID: <560E956A.6070700@cogentembedded.com> Date: Fri, 2 Oct 2015 17:32:10 +0300 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/2/2015 5:26 PM, Måns Rullgård wrote: >>> Some SoCs have a UART with a non-standard register layout. This >>> allows the debug console to work with these. >> >>> Signed-off-by: Mans Rullgard >>> --- >>> I would have preferred a more accurate description of the UART, but I've >>> not managed to figure out who the vendor is. >> >> You haven't seem the Alchemy datasheets? I can send you some if so. > > I have. They don't say where Alchemy bought the UART block. In fact, seeing at least Au1550 databook googling for "alchemy databook". The UART registers are described there. Perhaps, it's not accurate enought for your needs, though... >>> --- >>> arch/arm/Kconfig.debug | 4 ++++ >>> arch/arm/include/debug/8250.S | 12 ++++++++++++ >>> 2 files changed, 16 insertions(+) >>> >>> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug >>> index 0cfd7f9..8d5c837 100644 >>> --- a/arch/arm/Kconfig.debug >>> +++ b/arch/arm/Kconfig.debug >>> @@ -1597,6 +1597,10 @@ config DEBUG_UART_8250_WORD >>> DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \ >>> DEBUG_BRCMSTB_UART >>> >>> +config DEBUG_UART_8250_AU >>> + bool "8250 UART has Alchemy register layout" >>> + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 >>> + >> >> So Alchemy UART got reused on ARM? > > The UART is actually a Palmchip IP core used by several SoC companies. Hm, how have you figured out that;s Palmchip if the Alchemy databooks are silent about that? :-) MBR, Sergei