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Tue, 18 Jun 2024 10:19:27 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.11.0-alpha0-522-ga39cca1d5-fm-20240610.002-ga39cca1d MIME-Version: 1.0 Message-Id: <561150e8-e856-4993-8026-4872b1a8d55a@app.fastmail.com> In-Reply-To: References: <20240522-loongarch-v1-0-1407e0b69678@flygoat.com> <20240522-loongarch-v1-7-1407e0b69678@flygoat.com> <630db8ca-d954-4fe7-b113-0057d5ba9563@gmx.de> Date: Tue, 18 Jun 2024 15:19:04 +0100 From: "Jiaxun Yang" To: "Heinrich Schuchardt" Cc: u-boot@lists.denx.de, "Simon Glass" , "Tom Rini" , "Ilias Apalodimas" Subject: Re: [PATCH 07/16] LoongArch: lib: General routines Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean =E5=9C=A82024=E5=B9=B46=E6=9C=8816=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8B=E5= =8D=885:00=EF=BC=8CHeinrich Schuchardt=E5=86=99=E9=81=93=EF=BC=9A [...] > The "LoongArch Reference Manual" is available at: > > https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.h= tml#_cacop > > What irritates me in > 2.1.7.1. Cache Coherency Maintenance of Instruction Cache > is the word *can*: > > The Cache coherency maintenance between the instruction Cache and the > data Cache within the processor core *can* be implemented as hardware > maintenance. > > Maybe you have to consult the Chinese version. > > =E5=A4=84=E7=90=86=E5=99=A8=E6=A0=B8=E5=86=85=E9=83=A8=E6=8C=87=E4=BB=A4= Cache =E4=B8=8E=E6=95=B0=E6=8D=AE Cache =E4=B9=8B=E9=97=B4=E7=9A=84=E7=BC= =93=E5=AD=98=E4=B8=80=E8=87=B4=E6=80=A7=E7=BB=B4=E6=8A=A4=E5=8F=AF=E4=BB= =A5=E5=AE=9E=E7=8E=B0=E4=B8=BA=E7=A1=AC=E4=BB=B6=E7=BB=B4=E6=8A=A4 > > The cache consistency maintenance between the instruction cache and da= ta > cache inside the processor core *can* be implemented as hardware > maintenance. Hi Heinrich, Thanks for the investigation! Impressive effort on decrypting Chinese semantics :-) I had consulted Loongson folks, and they told me that all current hardwa= re implementation do have I/D cache coherency maintained by hardware, see implementation[1] in kernel. For dcache I'll implement it with cac_op. Thanks [1]: https://elixir.bootlin.com/linux/v6.9.5/source/arch/loongarch/mm/ca= che.c > > Best regards > > Heinrich --=20 - Jiaxun