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From: Richard Henderson <rth@twiddle.net>
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Date: Wed, 7 Oct 2015 20:46:30 +1100
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Subject: Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE,
 EQ}Z instead of MOVN/MOVZ
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To: James Hogan <james.hogan@imgtec.com>, qemu-devel@nongnu.org
Cc: Leon Alrae <leon.alrae@imgtec.com>, Aurelien Jarno <aurelien@aurel32.net>

On 10/02/2015 10:24 PM, James Hogan wrote:
> Extend MIPS movcond implementation to support the SELNEZ/SELEQZ
> instructions introduced in MIPS r6 (where MOVN/MOVZ have been removed).
>
> Whereas the "MOVN/MOVZ rd, rs, rt" instructions have the following
> semantics:
>   rd = [!]rt ? rs : rd
>
> The "SELNEZ/SELEQZ rd, rs, rt" instructions are slightly different:
>   rd = [!]rt ? rs : 0
>
> First we ensure that if one of the movcond input values is zero that it
> comes last (we can swap the input arguments if we invert the condition).
> This is so that it can exactly match one of the SELNEZ/SELEQZ
> instructions and avoid the need to emit the other one.
>
> Otherwise we emit the opposite instruction first into a temporary
> register, and OR that into the result:
>   SELNEZ/SELEQZ  TMP1, v2, c1
>   SELEQZ/SELNEZ  ret, v1, c1
>   OR             ret, ret, TMP1
>
> Which does the following:
>   ret = cond ? v1 : v2
>
> Signed-off-by: James Hogan<james.hogan@imgtec.com>
> Cc: Richard Henderson<rth@twiddle.net>
> Cc: Aurelien Jarno<aurelien@aurel32.net>

Reviewed-by: Richard Henderson <rth@twiddle.net>


>      { INDEX_op_brcond_i32, { "rZ", "rZ" } },
> +#if !use_mips32r6_instructions
>      { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
> +#else
> +    { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
> +#endif


The only thing I'd change is preferring positive tests to negative ones.  So 
swap the order of these lines, and the sense of the #if.

Leon, do you want to take this as a mips maintainer, or shall I as tcg maintainer?


r~