From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Thu, 08 Oct 2015 17:09:20 +0100 Subject: [PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode In-Reply-To: <20151008155655.GO17192@e104818-lin.cambridge.arm.com> References: <1443803874-9566-1-git-send-email-marc.zyngier@arm.com> <20151008155655.GO17192@e104818-lin.cambridge.arm.com> Message-ID: <56169530.9030902@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 08/10/15 16:56, Catalin Marinas wrote: > On Fri, Oct 02, 2015 at 05:37:49PM +0100, Marc Zyngier wrote: >> Recent evolutions of the ARM Trusted Firmware have outlined issues >> when the system is equipped with a GICv3 interrupt controller, but the >> firmware has decided to restrict it to GICv2 compatibility mode. >> >> In this mode, system registers cannot be enabled, and the firmware is >> expected to pass a GICv2 description (DT or ACPI tables). >> >> This series makes sure that system register access is checked at EL2 >> setup time and when the feature detection is performed. Additionally, >> the GICv2 driver checks that system registers are disabled, and warns >> if they are enabled. >> >> The booting requirements are also updated to make the above explicit. >> >> Marc Zyngier (5): >> arm64: el2_setup: Make sure ICC_SRE_EL2.SRE sticks before using GICv3 >> sysregs >> irqchip/gic-v3: Make gic_enable_sre an inline function >> arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling >> ARM64_HAS_SYSREG_GIC_CPUIF >> irqchip/gic: Warn if GICv3 system registers are enabled >> arm64: Update booting requirements for GICv3 in GICv2 mode >> >> Documentation/arm64/booting.txt | 11 ++++++++++- >> arch/arm64/kernel/cpufeature.c | 19 ++++++++++++++++++- >> arch/arm64/kernel/head.S | 2 ++ >> drivers/irqchip/irq-gic-v3.c | 32 +++++++++----------------------- >> drivers/irqchip/irq-gic.c | 15 +++++++++++++++ >> include/linux/irqchip/arm-gic-v3.h | 16 ++++++++++++++++ >> 6 files changed, 70 insertions(+), 25 deletions(-) > > Reviewed-by: Catalin Marinas > > How do you plan to merge these patches? I'm fine for them to go via the > irqchip maintainers since they are all GIC related. I guess we can direct this via tip if Thomas is OK with it. Thanks, M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757213AbbJHQJY (ORCPT ); Thu, 8 Oct 2015 12:09:24 -0400 Received: from foss.arm.com ([217.140.101.70]:35343 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753180AbbJHQJX (ORCPT ); Thu, 8 Oct 2015 12:09:23 -0400 Message-ID: <56169530.9030902@arm.com> Date: Thu, 08 Oct 2015 17:09:20 +0100 From: Marc Zyngier Organization: ARM Ltd User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.7.0 MIME-Version: 1.0 To: Catalin Marinas CC: Thomas Gleixner , Jason Cooper , Will Deacon , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode References: <1443803874-9566-1-git-send-email-marc.zyngier@arm.com> <20151008155655.GO17192@e104818-lin.cambridge.arm.com> In-Reply-To: <20151008155655.GO17192@e104818-lin.cambridge.arm.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/10/15 16:56, Catalin Marinas wrote: > On Fri, Oct 02, 2015 at 05:37:49PM +0100, Marc Zyngier wrote: >> Recent evolutions of the ARM Trusted Firmware have outlined issues >> when the system is equipped with a GICv3 interrupt controller, but the >> firmware has decided to restrict it to GICv2 compatibility mode. >> >> In this mode, system registers cannot be enabled, and the firmware is >> expected to pass a GICv2 description (DT or ACPI tables). >> >> This series makes sure that system register access is checked at EL2 >> setup time and when the feature detection is performed. Additionally, >> the GICv2 driver checks that system registers are disabled, and warns >> if they are enabled. >> >> The booting requirements are also updated to make the above explicit. >> >> Marc Zyngier (5): >> arm64: el2_setup: Make sure ICC_SRE_EL2.SRE sticks before using GICv3 >> sysregs >> irqchip/gic-v3: Make gic_enable_sre an inline function >> arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling >> ARM64_HAS_SYSREG_GIC_CPUIF >> irqchip/gic: Warn if GICv3 system registers are enabled >> arm64: Update booting requirements for GICv3 in GICv2 mode >> >> Documentation/arm64/booting.txt | 11 ++++++++++- >> arch/arm64/kernel/cpufeature.c | 19 ++++++++++++++++++- >> arch/arm64/kernel/head.S | 2 ++ >> drivers/irqchip/irq-gic-v3.c | 32 +++++++++----------------------- >> drivers/irqchip/irq-gic.c | 15 +++++++++++++++ >> include/linux/irqchip/arm-gic-v3.h | 16 ++++++++++++++++ >> 6 files changed, 70 insertions(+), 25 deletions(-) > > Reviewed-by: Catalin Marinas > > How do you plan to merge these patches? I'm fine for them to go via the > irqchip maintainers since they are all GIC related. I guess we can direct this via tip if Thomas is OK with it. Thanks, M. -- Jazz is not dead. It just smells funny...