From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Liuqiming (John)" <john.liuqiming@huawei.com>
Subject: Re: [PATCH] Remove a set operation for
 VCPU_KICK_SOFTIRQ when post interrupt to vm.
Date: Sat, 10 Oct 2015 17:55:37 +0800
Message-ID: <5618E099.1060600@huawei.com>
References: <1441637175-18070-1-git-send-email-john.liuqiming@huawei.com>
	<55ED9E00.2010105@huawei.com>
	<55EDBF4002000078000A07B1@prv-mh.provo.novell.com>
	<FAB5C136CA8BEA4DBEA2F641E3F536387FF83B09@SZXEMA504-MBX.china.huawei.com>
	<A9667DDFB95DB7438FA9D7D576C3D87E0AD999C1@SHSMSX104.ccr.corp.intel.com>
	<55EE5EF6.50406@huawei.com>
	<A9667DDFB95DB7438FA9D7D576C3D87E0ADB5D5B@SHSMSX104.ccr.corp.intel.com>
	<FAB5C136CA8BEA4DBEA2F641E3F536387FFC583E@SZXEMA504-MBX.china.huawei.com>
	<A9667DDFB95DB7438FA9D7D576C3D87E0ADB6311@SHSMSX104.ccr.corp.intel.com>
	<560362C4.4050500@huawei.com>
	<A9667DDFB95DB7438FA9D7D576C3D87E0ADB69D4@SHSMSX104.ccr.corp.intel.com>
	<5603A143.5060501@huawei.com>
	<A9667DDFB95DB7438FA9D7D576C3D87E0ADD37D6@SHSMSX104.ccr.corp.intel.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; Format="flowed"
Content-Transfer-Encoding: 7bit
Return-path: <xen-devel-bounces@lists.xen.org>
Received: from mail6.bemta14.messagelabs.com ([193.109.254.103])
	by lists.xen.org with esmtp (Exim 4.72)
	(envelope-from <john.liuqiming@huawei.com>) id 1Zkqsg-0000M2-9F
	for xen-devel@lists.xenproject.org; Sat, 10 Oct 2015 09:55:58 +0000
In-Reply-To: <A9667DDFB95DB7438FA9D7D576C3D87E0ADD37D6@SHSMSX104.ccr.corp.intel.com>
List-Unsubscribe: <http://lists.xen.org/cgi-bin/mailman/options/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=unsubscribe>
List-Post: <mailto:xen-devel@lists.xen.org>
List-Help: <mailto:xen-devel-request@lists.xen.org?subject=help>
List-Subscribe: <http://lists.xen.org/cgi-bin/mailman/listinfo/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=subscribe>
Sender: xen-devel-bounces@lists.xen.org
Errors-To: xen-devel-bounces@lists.xen.org
To: "Zhang, Yang Z" <yang.z.zhang@intel.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>, Jan Beulich <jbeulich@suse.com>, "Zhangwei (FF)" <zw.zhang@huawei.com>, "Hanweidong (Randy)" <hanweidong@huawei.com>
List-Id: xen-devel@lists.xenproject.org


On 2015/10/10 14:32, Zhang, Yang Z wrote:
> Zhang, Yang Z wrote on 2015-09-24:
>> Liuqiming (John) wrote on 2015-09-24:
>>>
>>> On 2015/9/24 11:25, Zhang, Yang Z wrote:
>>> it completed, the following vmentry will pick up the pending interrupt.
>>> If you send the ipi unconditionally, actually it is received by
>>> hypervisor and the interrupt handler dose nothing. You still rely on
>>> the vmentry to pick up the interrupt. My confusion is:  when
>>> vmentry, does physical CPU inject all interrupts on PIR into VM and
>>> clear POSTED_INTR_ON bit? Or just inject the highest index of PIR
>>> and may leave POSTED_INTR_ON bit being set to 1?
>> I need to say your understanding is wrong. What we need to do is sync
>> the pir to irr and let hardware or hypervisor to handle left part. So
>> our focus is how to sync pir to irr correctly and timely. We don't
>> care how the interrupt in PIR is injected to guest.
> Hi Qiming, is there any other question with it? Also, do you have any chance to test it?
>
> Best regards,
> Yang
   No other question.
   I have run some vm start-shutdown test, and haven't gotten a chance 
to test the performance.