From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [V6 4/4] libxc: expose xsaves/xgetbv1/xsavec to hvm guest Date: Mon, 12 Oct 2015 11:11:38 +0100 Message-ID: <561B875A.9090101@citrix.com> References: <1444630048-19411-1-git-send-email-shuai.ruan@linux.intel.com> <1444630048-19411-5-git-send-email-shuai.ruan@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1444630048-19411-5-git-send-email-shuai.ruan@linux.intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Shuai Ruan , xen-devel@lists.xen.org Cc: kevin.tian@intel.com, wei.liu2@citrix.com, Ian.Campbell@citrix.com, stefano.stabellini@eu.citrix.com, eddie.dong@intel.com, ian.jackson@eu.citrix.com, jbeulich@suse.com, jun.nakajima@intel.com, keir@xen.org List-Id: xen-devel@lists.xenproject.org On 12/10/15 07:07, Shuai Ruan wrote: > This patch exposes xsaves/xgetbv1/xsavec to hvm guest. > The reserved bits of eax/ebx/ecx/edx must be cleaned up > when call cpuid(0dh) with leaf 1 or 2..63. > > According to the spec the following bits must be reserved: > For leaf 1, bits 03-04/08-31 of ecx is reserved. Edx is reserved. > For leaf 2...63, bits 01-31 of ecx is reserved. Edx is reserved. > > Acked-by: Ian Campbell > Signed-off-by: Shuai Ruan This patch needs rebasing over c/s bf87f3a "tools/libxc: Improve efficiency of xc_cpuid_apply_policy()" > --- > tools/libxc/xc_cpuid_x86.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c > index e146a3e..b0d6ecc 100644 > --- a/tools/libxc/xc_cpuid_x86.c > +++ b/tools/libxc/xc_cpuid_x86.c > @@ -210,6 +210,10 @@ static void intel_xc_cpuid_policy( > } > > #define XSAVEOPT (1 << 0) > +#define XSAVEC (1 << 1) > +#define XGETBV1 (1 << 2) > +#define XSAVES (1 << 3) > +#define XSS_SUPPORT (1 << 0) > /* Configure extended state enumeration leaves (0x0000000D for xsave) */ > static void xc_cpuid_config_xsave( > xc_interface *xch, domid_t domid, uint64_t xfeature_mask, > @@ -246,8 +250,9 @@ static void xc_cpuid_config_xsave( > regs[1] = 512 + 64; /* FP/SSE + XSAVE.HEADER */ > break; > case 1: /* leaf 1 */ > - regs[0] &= XSAVEOPT; > - regs[1] = regs[2] = regs[3] = 0; > + regs[0] &= (XSAVEOPT | XSAVEC | XGETBV1 | XSAVES); The correct mask here depends on !info->hvm, to hide XSAVES from PV guests. > + regs[2] &= xfeature_mask; > + regs[3] = 0; > break; > case 2 ... 63: /* sub-leaves */ > if ( !(xfeature_mask & (1ULL << input[1])) ) > @@ -255,8 +260,11 @@ static void xc_cpuid_config_xsave( > regs[0] = regs[1] = regs[2] = regs[3] = 0; > break; > } > - /* Don't touch EAX, EBX. Also cleanup ECX and EDX */ > - regs[2] = regs[3] = 0; > + /* Don't touch EAX, EBX and cleanup EDX. > + * Bit 0 of ECX represent whether sub-leave is supported in IA32_XSS > + * msr or supported in XCR0.*/ > + regs[2] &= XSS_SUPPORT; No XSS features are currently supported, even in HVM guests. This should be unilaterally zero at the moment. ~Andrew > + regs[3] = 0; > break; > } > }