From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH] x86: hide MWAITX from PV domains Date: Tue, 13 Oct 2015 14:15:27 +0100 Message-ID: <561D03EF.2000102@citrix.com> References: <561D145002000078000AA892@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1ZlzQk-0005tT-85 for xen-devel@lists.xenproject.org; Tue, 13 Oct 2015 13:15:50 +0000 In-Reply-To: <561D145002000078000AA892@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich , xen-devel Cc: Keir Fraser List-Id: xen-devel@lists.xenproject.org On 13/10/15 13:25, Jan Beulich wrote: > Since MWAIT is hidden too. (Linux starting with 4.3 is making use of > that feature, and is checking for it without looking at the MWAIT one.) This is surely a Linux bug which wants fixing as well? > > Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper > > --- a/xen/arch/x86/traps.c > +++ b/xen/arch/x86/traps.c > @@ -964,6 +964,7 @@ void pv_cpuid(struct cpu_user_regs *regs > __clear_bit(X86_FEATURE_LWP % 32, &c); > __clear_bit(X86_FEATURE_NODEID_MSR % 32, &c); > __clear_bit(X86_FEATURE_TOPOEXT % 32, &c); > + __clear_bit(X86_FEATURE_MWAITX % 32, &c); > break; > > case 0x0000000a: /* Architectural Performance Monitor Features (Intel) */ > --- a/xen/include/asm-x86/cpufeature.h > +++ b/xen/include/asm-x86/cpufeature.h > @@ -140,6 +140,7 @@ > #define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ > #define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ > #define X86_FEATURE_DBEXT (6*32+26) /* data breakpoint extension */ > +#define X86_FEATURE_MWAITX (6*32+29) /* MWAIT extension (MONITORX/MWAITX) */ > > /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */ > #define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ > > >