diff for duplicates of <561E580D.4090706@gmail.com> diff --git a/a/1.txt b/N1/1.txt index b7323f2..81fb82c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -20,7 +20,7 @@ Applied, thanks. > clock-output-names = "clk32k"; > }; > -> + cpum_ck: oscillator@2 { +> + cpum_ck: oscillator at 2 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <0>; @@ -35,31 +35,31 @@ Applied, thanks. > status = "disabled"; > }; > + -> + mmsys: clock-controller@14000000 { +> + mmsys: clock-controller at 14000000 { > + compatible = "mediatek,mt8173-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + -> + imgsys: clock-controller@15000000 { +> + imgsys: clock-controller at 15000000 { > + compatible = "mediatek,mt8173-imgsys", "syscon"; > + reg = <0 0x15000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + -> + vdecsys: clock-controller@16000000 { +> + vdecsys: clock-controller at 16000000 { > + compatible = "mediatek,mt8173-vdecsys", "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + -> + vencsys: clock-controller@18000000 { +> + vencsys: clock-controller at 18000000 { > + compatible = "mediatek,mt8173-vencsys", "syscon"; > + reg = <0 0x18000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + -> + vencltsys: clock-controller@19000000 { +> + vencltsys: clock-controller at 19000000 { > + compatible = "mediatek,mt8173-vencltsys", "syscon"; > + reg = <0 0x19000000 0 0x1000>; > + #clock-cells = <1>; diff --git a/a/content_digest b/N1/content_digest index 83ce715..0f95c4a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,21 +1,9 @@ "ref\01439200228-318-1-git-send-email-jamesjj.liao@mediatek.com\0" "ref\01439200228-318-10-git-send-email-jamesjj.liao@mediatek.com\0" - "From\0Matthias Brugger <matthias.bgg@gmail.com>\0" - "Subject\0Re: [PATCH v7 9/9] arm64: dts: mt8173: Add subsystem clock controller device nodes\0" + "From\0matthias.bgg@gmail.com (Matthias Brugger)\0" + "Subject\0[PATCH v7 9/9] arm64: dts: mt8173: Add subsystem clock controller device nodes\0" "Date\0Wed, 14 Oct 2015 15:26:37 +0200\0" - "To\0James Liao <jamesjj.liao@mediatek.com>" - Mike Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - " Heiko Stubner <heiko@sntech.de>\0" - "Cc\0srv_heupstream@mediatek.com" - Daniel Kurtz <djkurtz@chromium.org> - Ricky Liang <jcliang@chromium.org> - Rob Herring <robh+dt@kernel.org> - Sascha Hauer <kernel@pengutronix.de> - devicetree@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - " linux-mediatek@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "\n" @@ -40,7 +28,7 @@ "> \t\tclock-output-names = \"clk32k\";\n" "> \t};\n" ">\n" - "> +\tcpum_ck: oscillator@2 {\n" + "> +\tcpum_ck: oscillator at 2 {\n" "> +\t\tcompatible = \"fixed-clock\";\n" "> +\t\t#clock-cells = <0>;\n" "> +\t\tclock-frequency = <0>;\n" @@ -55,31 +43,31 @@ "> \t\t\tstatus = \"disabled\";\n" "> \t\t};\n" "> +\n" - "> +\t\tmmsys: clock-controller@14000000 {\n" + "> +\t\tmmsys: clock-controller at 14000000 {\n" "> +\t\t\tcompatible = \"mediatek,mt8173-mmsys\", \"syscon\";\n" "> +\t\t\treg = <0 0x14000000 0 0x1000>;\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\timgsys: clock-controller@15000000 {\n" + "> +\t\timgsys: clock-controller at 15000000 {\n" "> +\t\t\tcompatible = \"mediatek,mt8173-imgsys\", \"syscon\";\n" "> +\t\t\treg = <0 0x15000000 0 0x1000>;\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tvdecsys: clock-controller@16000000 {\n" + "> +\t\tvdecsys: clock-controller at 16000000 {\n" "> +\t\t\tcompatible = \"mediatek,mt8173-vdecsys\", \"syscon\";\n" "> +\t\t\treg = <0 0x16000000 0 0x1000>;\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tvencsys: clock-controller@18000000 {\n" + "> +\t\tvencsys: clock-controller at 18000000 {\n" "> +\t\t\tcompatible = \"mediatek,mt8173-vencsys\", \"syscon\";\n" "> +\t\t\treg = <0 0x18000000 0 0x1000>;\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tvencltsys: clock-controller@19000000 {\n" + "> +\t\tvencltsys: clock-controller at 19000000 {\n" "> +\t\t\tcompatible = \"mediatek,mt8173-vencltsys\", \"syscon\";\n" "> +\t\t\treg = <0 0x19000000 0 0x1000>;\n" "> +\t\t\t#clock-cells = <1>;\n" @@ -89,4 +77,4 @@ ">\n" > -de32e334493d85619b509c830afe4af04512dc7595a9489c25290b898f99568f +44cfccfad9ff96b522a19434e5834d88ca0038f8fca23b107eebfcda0f92ea40
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