From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH 3/4] x86: don't use FPU instructions when there is no FPU Date: Wed, 14 Oct 2015 15:30:45 +0100 Message-ID: <561E6715.70509@citrix.com> References: <561E734D02000078000AAEC5@prv-mh.provo.novell.com> <561E753602000078000AAF09@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1ZmN4s-00050o-Jz for xen-devel@lists.xenproject.org; Wed, 14 Oct 2015 14:30:50 +0000 In-Reply-To: <561E753602000078000AAF09@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich , xen-devel Cc: Keir Fraser List-Id: xen-devel@lists.xenproject.org On 14/10/15 14:31, Jan Beulich wrote: > --- a/xen/include/asm-x86/cpufeature.h > +++ b/xen/include/asm-x86/cpufeature.h > @@ -170,6 +170,7 @@ > #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1 > #define CPUID5_ECX_INTERRUPT_BREAK 0x2 > > +#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) This distinguishes only between an onboard fpu or an original x87 co-processor. It does not represent the presence or absence of an fpu. Looking at the Xeon Phi documentation (http://download-software.intel.com/sites/default/files/forum/278102/327364001en.pdf), it has this feature bit set, although it does have MMX clear. Interestingly however, a Phi's default MXCSR value ix 0x20000h and will #GP at any attempt to clear bit 21, which means fpu_init() will unconditionally blow up on such a system. I am not aware of a bit which signifies the absence of FPU capabilities. Until there is, I don't think changes along these lines are a safe way to go. ~Andrew