From mboxrd@z Thu Jan 1 00:00:00 1970 From: julien.grall@citrix.com (Julien Grall) Date: Thu, 15 Oct 2015 10:58:56 +0100 Subject: [Xen-devel] xen,arm: enable cpu_hotplug In-Reply-To: <561F78A4.7060507@citrix.com> References: <561EE3E5.2000105@citrix.com> <1444898398.1607.18.camel@citrix.com> <561F78A4.7060507@citrix.com> Message-ID: <561F78E0.2070004@citrix.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 15/10/15 10:57, Julien Grall wrote: > Hi Ian, > > On 15/10/15 09:39, Ian Campbell wrote: >> On Thu, 2015-10-15 at 00:23 +0100, Julien Grall wrote: >>> My second point is related to how Xen is handling interrupt with vCPU. >>> When PSCI off is called, we will set the _VFP_down flag. This flag is >>> used in vgic_vcpu_inject_irq and when it's set the interrupt will be >>> ignored and stay active on the HW GIC forever. If the vCPU is coming >>> back online, this interrupt will never be received. AFAIU the spec, the >>> interrupt is expected to stay pending on the distributor side and will >>> be receive when the vCPU will come back or migrate to another vCPU. A >>> similar problem can happen when the vCPU is powered on again because we >>> clear all the interrupt state related to vCPU (see >>> vgic_clear_pending_irqs). >> >> Is there also an interaction with our implementation of ITARGETSR of >> picking the lowest set bit? e.g. if an IRQ has target 0x6 (targeting CPU 1 >> and CPU2) we will choose CPU 1. If CPU 1 is then unplugged, will we end up >> targeting CPU 2 or the now-offline CPU 1? In the latter case the lack of >> interrupts might be considered surprising? > > I though about it when I wrote the mail yesterday night. > > From the spec section 1.4.3 (ARM IHI 0048B.b): > > "The ARM GIC architecture does not guarantee that a 1-N interrupt is > presented to: > ? all processors listed in the target processor list > ? an enabled interface, where at least one interface is enabled." > > AFAIU this paragraph, it means that there is no guarantee to receive an > interrupt if the target mask contain a vCPU offline. Hmmm I may not have been clear here. I meant that the interrupt will stay pending in the distributor but not received by the guest. -- Julien Grall From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [Xen-devel] xen,arm: enable cpu_hotplug Date: Thu, 15 Oct 2015 10:58:56 +0100 Message-ID: <561F78E0.2070004@citrix.com> References: <561EE3E5.2000105@citrix.com> <1444898398.1607.18.camel@citrix.com> <561F78A4.7060507@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <561F78A4.7060507@citrix.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Ian Campbell , Stefano Stabellini , xen-devel@lists.xensource.com Cc: linux-arm-kernel@lists.infradead.org List-Id: xen-devel@lists.xenproject.org T24gMTUvMTAvMTUgMTA6NTcsIEp1bGllbiBHcmFsbCB3cm90ZToKPiBIaSBJYW4sCj4gCj4gT24g MTUvMTAvMTUgMDk6MzksIElhbiBDYW1wYmVsbCB3cm90ZToKPj4gT24gVGh1LCAyMDE1LTEwLTE1 IGF0IDAwOjIzICswMTAwLCBKdWxpZW4gR3JhbGwgd3JvdGU6Cj4+PiBNeSBzZWNvbmQgcG9pbnQg aXMgcmVsYXRlZCB0byBob3cgWGVuIGlzIGhhbmRsaW5nIGludGVycnVwdCB3aXRoIHZDUFUuIAo+ Pj4gV2hlbiBQU0NJIG9mZiBpcyBjYWxsZWQsIHdlIHdpbGwgc2V0IHRoZSBfVkZQX2Rvd24gZmxh Zy4gVGhpcyBmbGFnIGlzIAo+Pj4gdXNlZCBpbiB2Z2ljX3ZjcHVfaW5qZWN0X2lycSBhbmQgd2hl biBpdCdzIHNldCB0aGUgaW50ZXJydXB0IHdpbGwgYmUgCj4+PiBpZ25vcmVkIGFuZCBzdGF5IGFj dGl2ZSBvbiB0aGUgSFcgR0lDIGZvcmV2ZXIuIElmIHRoZSB2Q1BVIGlzIGNvbWluZyAKPj4+IGJh Y2sgb25saW5lLCB0aGlzIGludGVycnVwdCB3aWxsIG5ldmVyIGJlIHJlY2VpdmVkLiBBRkFJVSB0 aGUgc3BlYywgdGhlIAo+Pj4gaW50ZXJydXB0IGlzIGV4cGVjdGVkIHRvIHN0YXkgcGVuZGluZyBv biB0aGUgZGlzdHJpYnV0b3Igc2lkZSBhbmQgd2lsbCAKPj4+IGJlIHJlY2VpdmUgd2hlbiB0aGUg dkNQVSB3aWxsIGNvbWUgYmFjayBvciBtaWdyYXRlIHRvIGFub3RoZXIgdkNQVS4gQSAKPj4+IHNp bWlsYXIgcHJvYmxlbSBjYW4gaGFwcGVuIHdoZW4gdGhlIHZDUFUgaXMgcG93ZXJlZCBvbiBhZ2Fp biBiZWNhdXNlIHdlIAo+Pj4gY2xlYXIgYWxsIHRoZSBpbnRlcnJ1cHQgc3RhdGUgcmVsYXRlZCB0 byB2Q1BVIChzZWUKPj4+IHZnaWNfY2xlYXJfcGVuZGluZ19pcnFzKS4KPj4KPj4gSXMgdGhlcmUg YWxzbyBhbiBpbnRlcmFjdGlvbiB3aXRoIG91ciBpbXBsZW1lbnRhdGlvbiBvZiBJVEFSR0VUU1Ig b2YKPj4gcGlja2luZyB0aGUgbG93ZXN0IHNldCBiaXQ/IGUuZy4gaWYgYW4gSVJRIGhhcyB0YXJn ZXQgMHg2ICh0YXJnZXRpbmcgQ1BVIDEKPj4gYW5kIENQVTIpIHdlIHdpbGwgY2hvb3NlIENQVSAx LiBJZiBDUFUgMSBpcyB0aGVuIHVucGx1Z2dlZCwgd2lsbCB3ZSBlbmQgdXAKPj4gdGFyZ2V0aW5n IENQVSAyIG9yIHRoZSBub3ctb2ZmbGluZSBDUFUgMT8gSW4gdGhlIGxhdHRlciBjYXNlIHRoZSBs YWNrIG9mCj4+IGludGVycnVwdHMgbWlnaHQgYmUgY29uc2lkZXJlZCBzdXJwcmlzaW5nPwo+IAo+ IEkgdGhvdWdoIGFib3V0IGl0IHdoZW4gSSB3cm90ZSB0aGUgbWFpbCB5ZXN0ZXJkYXkgbmlnaHQu Cj4gCj4gRnJvbSB0aGUgc3BlYyBzZWN0aW9uIDEuNC4zIChBUk0gSUhJIDAwNDhCLmIpOgo+IAo+ ICJUaGUgQVJNIEdJQyBhcmNoaXRlY3R1cmUgZG9lcyBub3QgZ3VhcmFudGVlIHRoYXQgYSAxLU4g aW50ZXJydXB0IGlzCj4gcHJlc2VudGVkIHRvOgo+IOKAlCBhbGwgcHJvY2Vzc29ycyBsaXN0ZWQg aW4gdGhlIHRhcmdldCBwcm9jZXNzb3IgbGlzdAo+IOKAlCBhbiBlbmFibGVkIGludGVyZmFjZSwg d2hlcmUgYXQgbGVhc3Qgb25lIGludGVyZmFjZSBpcyBlbmFibGVkLiIKPiAKPiBBRkFJVSB0aGlz IHBhcmFncmFwaCwgaXQgbWVhbnMgdGhhdCB0aGVyZSBpcyBubyBndWFyYW50ZWUgdG8gcmVjZWl2 ZSBhbgo+IGludGVycnVwdCBpZiB0aGUgdGFyZ2V0IG1hc2sgY29udGFpbiBhIHZDUFUgb2ZmbGlu ZS4KCkhtbW0gSSBtYXkgbm90IGhhdmUgYmVlbiBjbGVhciBoZXJlLiBJIG1lYW50IHRoYXQgdGhl IGludGVycnVwdCB3aWxsCnN0YXkgcGVuZGluZyBpbiB0aGUgZGlzdHJpYnV0b3IgYnV0IG5vdCBy ZWNlaXZlZCBieSB0aGUgZ3Vlc3QuCgotLSAKSnVsaWVuIEdyYWxsCgpfX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcg bGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmlu ZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==