From: slash.tmp@free.fr (Mason)
To: linux-arm-kernel@lists.infradead.org
Subject: l2c: Kernel panic in l2c310_enable() in non-secure mode
Date: Fri, 16 Oct 2015 11:51:13 +0200 [thread overview]
Message-ID: <5620C891.9040707@free.fr> (raw)
In-Reply-To: <561F88F4.40401@sigmadesigns.com>
On 15/10/2015 13:07, Marc Gonzalez wrote:
> One more question on this topic:
>
> When Linux sees L310_AUX_CTRL_FULL_LINE_ZERO set, it then enables:
>
> bit3 = Write full line of zeros mode
> bit2 = L1 Prefetch enable
> bit1 = L2 Prefetch hint enable
>
> Why are the "prefetch enable" features bundled in the operation?
Russell,
The prefetch enable bits were introduced in commit 8ef418c7178fa
("ARM: l2c: trial at enabling some Cortex-A9 optimisations")
I didn't find a ML thread discussing that patch. Whenever possible,
could you provide some insight into the rationale leading you to
set bits 1 and 2 along with bit 3? (The ARM integrator here tends
to think the two concepts are somewhat orthogonal.)
Regards.
next prev parent reply other threads:[~2015-10-16 9:51 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-14 14:17 l2c: Kernel panic in l2c310_enable() in non-secure mode Marc Gonzalez
2015-10-14 14:47 ` Marc Gonzalez
2015-10-14 17:06 ` Rob Herring
2015-10-15 8:56 ` Marc Gonzalez
2015-10-15 9:09 ` Russell King - ARM Linux
2015-10-14 17:47 ` Russell King - ARM Linux
2015-10-14 20:28 ` Mason
2015-10-15 10:00 ` Marc Gonzalez
2015-10-15 11:07 ` Marc Gonzalez
2015-10-16 9:51 ` Mason [this message]
2015-10-14 17:45 ` Russell King - ARM Linux
2015-10-14 19:34 ` Mason
2015-10-14 20:19 ` Peter Maydell
2015-10-14 21:08 ` Russell King - ARM Linux
2015-10-15 8:27 ` Marc Gonzalez
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