Re: [PATCH] x86/ept: defer enabling of EPT A/D bit until PML get enabled.

[Andrew Cooper <andrew.cooper3@citrix.com>]

On 16/10/15 10:27, Jan Beulich wrote:
>>>> On 16.10.15 at 11:17, <kai.huang@linux.intel.com> wrote:
>> On 10/16/2015 04:17 PM, Jan Beulich wrote:
>>>>>> On 16.10.15 at 04:21, <kai.huang@linux.intel.com> wrote:
>>>> +void vmx_domain_update_eptp(struct domain *d)
>>>> +{
>>>> +    struct p2m_domain *p2m = p2m_get_hostp2m(d);
>>>> +    struct vcpu *v;
>>>> +
>>>> +    ASSERT(atomic_read(&d->pause_count));
>>> This should imo check controller_pause_count.
>> This function is called between domain_pause and domain_unpause, and 
>> domain_pause increases d->pause_count, not d->controller_pause_count, so 
>> we should check d->pause_count, right?
> Ah, okay - I thought the pause was tool stack initiated.

ept_enable_pml() is the subject of p2m->enable_hardware_log_dirty(),
which happens during runtime with logdirty ops, etc.

~Andrew