From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52952) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zn6Nu-0004da-HP for qemu-devel@nongnu.org; Fri, 16 Oct 2015 10:53:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zn6Nr-00026d-BU for qemu-devel@nongnu.org; Fri, 16 Oct 2015 10:53:30 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:27022) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zn6Nr-00025o-4S for qemu-devel@nongnu.org; Fri, 16 Oct 2015 10:53:27 -0400 References: <1444049296-19715-1-git-send-email-yongbok.kim@imgtec.com> From: Leon Alrae Message-ID: <56210F51.3070105@imgtec.com> Date: Fri, 16 Oct 2015 15:53:05 +0100 MIME-Version: 1.0 In-Reply-To: <1444049296-19715-1-git-send-email-yongbok.kim@imgtec.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-mips: Add more reg numbers for RDHWR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim , qemu-devel@nongnu.org Cc: aurelien@aurel32.net On 05/10/15 13:48, Yongbok Kim wrote: > Add more register numbers for RDHWR Could the commit message say which registers exactly this patch is adding? > Add check_hwrena() to simplify access control checkings. > Add RDHWR support to microMIPS R6 > > Signed-off-by: Yongbok Kim > --- > @@ -1357,6 +1357,12 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) > { > uint32_t mask = 0x0000000F; > > + if (env->CP0_Config1 & (1 << CP0C1_PC)) { > + mask |= (1 << 4); > + } I think we should check also for ISA_MIPS32R6 here. The access to CP0.PerfCnt via RDHWR was added in R6 and before that the register number 4 in HWREna was reserved. Otherwise looks good to me. Thanks, Leon