From mboxrd@z Thu Jan 1 00:00:00 1970 From: Archit Taneja Subject: Re: [PATCH 1/2] clk: qcom: clk-rcg: Add customized clk_ops for DSI RCGs Date: Mon, 19 Oct 2015 10:15:36 +0530 Message-ID: <56247570.5040200@codeaurora.org> References: <1444827285-25233-1-git-send-email-architt@codeaurora.org> <1444827285-25233-2-git-send-email-architt@codeaurora.org> <20151016220538.GB10182@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from smtp.codeaurora.org ([198.145.29.96]:33543 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751109AbbJSEpl (ORCPT ); Mon, 19 Oct 2015 00:45:41 -0400 In-Reply-To: <20151016220538.GB10182@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, robdclark@gmail.com On 10/17/2015 03:35 AM, Stephen Boyd wrote: > On 10/14, Archit Taneja wrote: >> DSI specific RCG clocks required customized clk_ops. There are >> a total of 4 RCGs per DSI block: DSI, BYTE, ESC and PIXEL. >> >> There are a total of 2 clocks coming from the DSI PLL, which serve as >> inputs to these RCGs. The BYTE and ESC RCGs are fed by one of the >> post dividers of DSI1 or DSI2 PLLs, and the DSI and PIXEL RCGs are fed by >> another divider of the PLL. >> >> In each of the 2 groups above, only one of the clocks sets its parent. >> These are BYTE RCG and DSI RCG for each of the groups respectively, as >> shown in the diagram below. >> >> The DSI and BYTE RCGs serve as bypass clocks. We create a new set of ops >> clk_rcg_bypass2_ops, which are like the regular bypass ops, but don't >> take in a freq table, since the DSI driver using these clocks is >> parent-able. >> >> The PIXEL RCG needs to derive the required pixel clock using dsixpll. >> It parses a m/n frac table to retrieve the correct clock. >> >> The ESC RCG doesn't have a frac M/N block, it can just apply a pre- >> divider. Its ops simply check if the required clock rate can be >> achieved by the pre-divider. >> >> +-------------------+ >> | |---dsixpllbyte---o---> To byte RCG >> | | | (sets parent rate) >> | | | >> | | | >> | DSI 1/2 PLL | | >> | | o---> To esc RCG >> | | (doesn't set parent rate) >> | | >> | |----dsixpll-----o---> To dsi RCG >> +-------------------+ | (sets parent rate) >> ( x = 1, 2 ) | >> | >> o---> To pixel rcg >> (doesn't set parent rate) >> >> Signed-off-by: Archit Taneja >> --- > > Applied to clk-next + Thanks for the clean up! Archit > > ----8<---- > diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c > index 46ff9f25cd97..bfbb28f450c2 100644 > --- a/drivers/clk/qcom/clk-rcg.c > +++ b/drivers/clk/qcom/clk-rcg.c > @@ -564,7 +564,7 @@ static int clk_rcg_bypass2_set_rate(struct clk_hw *hw, unsigned long rate, > > ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); > if (ret) > - goto err; > + return ret; > > src = ns_to_src(&rcg->s, ns); > f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1; > @@ -576,7 +576,6 @@ static int clk_rcg_bypass2_set_rate(struct clk_hw *hw, unsigned long rate, > } > } > > -err: > return -EINVAL; > } > > @@ -636,7 +635,7 @@ static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate, > > ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); > if (ret) > - goto err; > + return ret; > > src = ns_to_src(&rcg->s, ns); > f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1; > @@ -662,7 +661,6 @@ static int clk_rcg_pixel_set_rate(struct clk_hw *hw, unsigned long rate, > return __clk_rcg_set_rate(rcg, &f); > } > > -err: > return -EINVAL; > } > > @@ -711,7 +709,7 @@ static int clk_rcg_esc_set_rate(struct clk_hw *hw, unsigned long rate, > > ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); > if (ret) > - goto err; > + return ret; > > ns = ns_to_src(&rcg->s, ns); > > @@ -729,7 +727,6 @@ static int clk_rcg_esc_set_rate(struct clk_hw *hw, unsigned long rate, > return __clk_rcg_set_rate(rcg, &f); > } > > -err: > return -EINVAL; > } > > -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation