From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49372) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZoDck-0001KA-U2 for qemu-devel@nongnu.org; Mon, 19 Oct 2015 12:49:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZoDch-0006B8-Mr for qemu-devel@nongnu.org; Mon, 19 Oct 2015 12:49:26 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:64819) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZoDch-0006B1-H4 for qemu-devel@nongnu.org; Mon, 19 Oct 2015 12:49:23 -0400 References: <1440591140-95670-1-git-send-email-petar.jovanovic@rt-rk.com> <20151011203059.GA16705@aurel32.net> <56251CFA.1010508@imgtec.com> From: Leon Alrae Message-ID: <56251F0C.5040205@imgtec.com> Date: Mon, 19 Oct 2015 17:49:16 +0100 MIME-Version: 1.0 In-Reply-To: <56251CFA.1010508@imgtec.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Petar Jovanovic , qemu-devel@nongnu.org, petar.jovanovic@imgtec.com, Aurelien Jarno Oops my email client dropped Aurelien's email from CC for some reason... (adding back) On 19/10/15 17:40, Leon Alrae wrote: > On 11/10/15 21:30, Aurelien Jarno wrote: >> (sorry for the late answer) >> >> On 2015-08-26 14:12, Petar Jovanovic wrote: >>> From: Petar Jovanovic >>> >>> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither >>> they require any particular mode for its FPU. This patch removes the checks >>> that may break a program that uses these instructions. >> >> That is correct. That said these instructions do require at least a >> MIPS32R2 or a MIPS64R1 CPU. I guess we should add these checks now that >> check_cop1x do not guard them anymore. > > I suspect that this might too restrictive if we take into account also > legacy processors. As far as I know these instructions were already > present in MIPS IV implementations. I think it'll be safer if for the > pre-MIPS32R2 and pre-MIPS64R1 CPUs we keep the check_cop1x. (actually > I'm not certain if check_cop1x is correct, but at least we aren't > relaxing the previous restrictions too much). > > Regards, > Leon >