From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH 1/2] x86/ept: defer enabling of EPT A/D bit until PML get enabled. Date: Tue, 20 Oct 2015 11:01:20 +0100 Message-ID: <562610F0.4020308@citrix.com> References: <1445308486-25132-1-git-send-email-kai.huang@linux.intel.com> <1445308486-25132-2-git-send-email-kai.huang@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1445308486-25132-2-git-send-email-kai.huang@linux.intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Kai Huang , jbeulich@suse.com, george.dunlap@eu.citrix.com, kevin.tian@intel.com, jun.nakajima@intel.com, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 20/10/15 03:34, Kai Huang wrote: > Existing PML implementation turns on EPT A/D bit unconditionally if PML is > supported by hardware. This works but enabling of EPT A/D bit can be deferred > until PML get enabled. There's no point in enabling the extra feature for every > domain when we're not meaning to use it (yet). > > Also added ASSERT of domain having been paused to ept_flush_pml_buffers to make > it consistent with ept_enable{disable}_pml. > > Sanity live migration and GUI display were tested on Broadwell Machine. > > Signed-off-by: Kai Huang > Suggested-by: Jan Beulich Reviewed-by: Andrew Cooper