diff for duplicates of <5626130A.5090604@nvidia.com> diff --git a/a/1.txt b/N1/1.txt index cccbcad..4cd5846 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ On 20/10/15 00:30, Stephen Warren wrote: -> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> From: Stephen Warren <swarren@nvidia.com> > > Convert the binding to provide a PHY per lane, rather than a PHY per > "pad" block in the hardware. This will allow the driver to easily know @@ -14,7 +14,7 @@ On 20/10/15 00:30, Stephen Warren wrote: > Add an nvidia,ss-port-map register to allow configuration of the > XUSB_PADCTL_SS_PORT_MAP register. > -> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Stephen Warren <swarren@nvidia.com> > --- > Thierry, Jon, here's a start at where I think the XUSB padctl binding > should go. What are your thoughts on this approach? diff --git a/a/content_digest b/N1/content_digest index 1a928c8..4cd24a7 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,21 +1,20 @@ "ref\01445297442-21439-1-git-send-email-swarren@wwwdotorg.org\0" - "ref\01445297442-21439-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org\0" - "From\0Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "From\0Jon Hunter <jonathanh@nvidia.com>\0" "Subject\0Re: [RFC PATCH] dt: Tegra XUSB padctl: per-lane PHYs and USB lane map\0" "Date\0Tue, 20 Oct 2015 11:10:18 +0100\0" - "To\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>" - " Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" - "Cc\0Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>" - Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> - Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org> - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - " Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "To\0Stephen Warren <swarren@wwwdotorg.org>" + " Thierry Reding <thierry.reding@gmail.com>\0" + "Cc\0Alexandre Courbot <gnurou@gmail.com>" + Andrew Bresticker <abrestic@chromium.org> + Kishon Vijay Abraham I <kishon@ti.com> + <linux-tegra@vger.kernel.org> + <linux-kernel@vger.kernel.org> + " Stephen Warren <swarren@nvidia.com>\0" "\00:1\0" "b\0" "\n" "On 20/10/15 00:30, Stephen Warren wrote:\n" - "> From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> From: Stephen Warren <swarren@nvidia.com>\n" "> \n" "> Convert the binding to provide a PHY per lane, rather than a PHY per\n" "> \"pad\" block in the hardware. This will allow the driver to easily know\n" @@ -29,7 +28,7 @@ "> Add an nvidia,ss-port-map register to allow configuration of the\n" "> XUSB_PADCTL_SS_PORT_MAP register.\n" "> \n" - "> Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Stephen Warren <swarren@nvidia.com>\n" "> ---\n" "> Thierry, Jon, here's a start at where I think the XUSB padctl binding\n" "> should go. What are your thoughts on this approach?\n" @@ -318,4 +317,4 @@ "\n" Jon -b8e998d632b04106ae0e84bb8ec80b83c6b678569f8841f3ca0fe621d10be828 +84f1daed32cbf2682bf29dc2600de2725d08e1f82a5b6afb0ec9e785c5d5a727
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