From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58082) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zovht-0007Cx-7Z for qemu-devel@nongnu.org; Wed, 21 Oct 2015 11:53:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zovhp-0000Gm-Tn for qemu-devel@nongnu.org; Wed, 21 Oct 2015 11:53:41 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:10224) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zovhp-0000Gd-Nv for qemu-devel@nongnu.org; Wed, 21 Oct 2015 11:53:37 -0400 References: <1444953129-35040-1-git-send-email-yongbok.kim@imgtec.com> <1444953129-35040-5-git-send-email-yongbok.kim@imgtec.com> From: Leon Alrae Message-ID: <5627B500.5030006@imgtec.com> Date: Wed, 21 Oct 2015 16:53:36 +0100 MIME-Version: 1.0 In-Reply-To: <1444953129-35040-5-git-send-email-yongbok.kim@imgtec.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 4/4] mips: add gic support to malta List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim , qemu-devel@nongnu.org Cc: pbonzini@redhat.com, afaerber@suse.de, aurelien@aurel32.net On 16/10/15 00:52, Yongbok Kim wrote: > /* > * We have a circular dependency problem: pci_bus depends on isa_irq, > * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends > @@ -1155,7 +1218,11 @@ void mips_malta_init(MachineState *machine) > > /* Interrupt controller */ > /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */ > - s->i8259 = i8259_init(isa_bus, env->irq[2]); > + if (env->gic_irqs) { > + s->i8259 = i8259_init(isa_bus, env->gic_irqs[3]); Probably s->gic.gic_irqs[3].irq should be used here. BTW I think "gic_irqs" can be replaced with a better name, something like "irq_state". > + } else { > + s->i8259 = i8259_init(isa_bus, env->irq[2]); > + } > > isa_bus_irqs(isa_bus, s->i8259); > pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1); > @@ -1209,7 +1276,7 @@ static void mips_malta_machine_init(MachineClass *mc) > { > mc->desc = "MIPS Malta Core LV"; > mc->init = mips_malta_init; > - mc->max_cpus = 16; > + mc->max_cpus = 32; > mc->is_default = 1; > } > > diff --git a/target-mips/cpu.h b/target-mips/cpu.h > index 639ef37..fdd5643 100644 > --- a/target-mips/cpu.h > +++ b/target-mips/cpu.h > @@ -594,6 +594,7 @@ struct CPUMIPSState { > > const mips_def_t *cpu_model; > void *irq[8]; > + void **gic_irqs; I don't think CPUMIPSState need any information about gic external interrupts. Leon > QEMUTimer *timer; /* Internal timer */ > }; > >