From mboxrd@z Thu Jan 1 00:00:00 1970 From: Martin Peres Subject: Re: PWM-based voltage management input clock Date: Tue, 27 Oct 2015 01:47:08 +0200 Message-ID: <562EBB7C.3010701@free.fr> References: <55FC7081.7050007@free.fr> <20150918203051.GA23395@prokofiev.nvidia.com> <55FD8B70.6010704@free.fr> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <55FD8B70.6010704-GANU6spQydw@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Nouveau" To: Andy Ritger Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, gpu-public-documentation List-Id: nouveau.vger.kernel.org T24gMTkvMDkvMTUgMTk6MjEsIE1hcnRpbiBQZXJlcyB3cm90ZToKPiBPbiAxOC8wOS8xNSAyMzoz MCwgQW5keSBSaXRnZXIgd3JvdGU6Cj4+IFRoYW5rcywgTWFydGluLiAgSSdsbCB0cnkgdG8gZm9s bG93IHVwIG9uIHRoaXMgbmV4dCB3ZWVrIGFuZCBnZXQgeW91IAo+PiBhbiBhbnN3ZXIuICBXaGF0 IEdQVXMgaGF2ZSB5b3Ugb2JzZXJ2ZWQgdGhpcyBvbj8KPj4KPiBUaGFua3MgQW5keSwKPgo+IEFz IGZhciBhcyBJIGNhbiB0ZWxsLCBpdCBpcyB0aGUgY2FzZSBmb3IgYWxsIEdQVXMgdXNpbmcgdGhl IFBXTS1iYXNlZCAKPiB2b2x0YWdlIG1hbmFnZW1lbnQuIFRvIGJlIG1vcmUgc3BlY2lmaWMsIHdl IGhhdmUgc2VlbiB0aGlzIGJlaGF2aW91ciAKPiBvbiBhIEdLMTA2IChtb2JpbGUpLCBhIEdNMTE3 IGFuZCBhIEdNMjA0LgoKSSBndWVzcyB0aGlzIGhhcyBmZWxsIGludG8gdGhlIGNyYWNrcyA6KSBB bnkgdXBkYXRlcyBvbiB0aGlzPwoKVGhhbmtzLApNYXJ0aW4KX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX18KTm91dmVhdSBtYWlsaW5nIGxpc3QKTm91dmVhdUBs aXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cDovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFu L2xpc3RpbmZvL25vdXZlYXUK