From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38333) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr1fD-0000xt-RW for qemu-devel@nongnu.org; Tue, 27 Oct 2015 06:39:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zr1f6-0007cP-TY for qemu-devel@nongnu.org; Tue, 27 Oct 2015 06:39:35 -0400 Received: from [59.151.112.132] (port=58845 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr1f6-0007aN-Fe for qemu-devel@nongnu.org; Tue, 27 Oct 2015 06:39:28 -0400 References: <1445830158-20721-1-git-send-email-caoj.fnst@cn.fujitsu.com> <1445830158-20721-3-git-send-email-caoj.fnst@cn.fujitsu.com> <20151026100131-mutt-send-email-mst@redhat.com> <562E151C.1040208@cn.fujitsu.com> <20151026140916-mutt-send-email-mst@redhat.com> <562F4635.1060503@cn.fujitsu.com> <20151027114452-mutt-send-email-mst@redhat.com> From: Cao jin Message-ID: <562F5457.2050306@cn.fujitsu.com> Date: Tue, 27 Oct 2015 18:39:19 +0800 MIME-Version: 1.0 In-Reply-To: <20151027114452-mutt-send-email-mst@redhat.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 2/2] enable multi-function hot-add List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: izumi.taku@jp.fujitsu.com, alex.williamson@redhat.com, qemu-devel@nongnu.org Hi Michael Thanks for your quick response On 10/27/2015 05:47 PM, Michael S. Tsirkin wrote: > On Tue, Oct 27, 2015 at 05:39:01PM +0800, Cao jin wrote: >>>>> static >>>>> bool pcie_has_upstream_port(PCIDevice *dev) >>>>> { >>>>> PCIDevice *parent_dev = pci_bridge_get_device(pci_dev->bus); >>>>> >>>>> /* >>>>> * Device associated with an upstream port. >>>>> * As there are several types of these, it's easier to check the >>>>> * parent device: upstream ports are always connected to >>>>> * root or downstream ports. >>>>> */ >>>>> return parent_dev && >>>>> pci_is_express(parent_dev) && >>>>> parent_dev->exp.exp_cap && >>>>> (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || >>>>> pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); >>>>> } >>>>> >>>> >>>> Assume my understanding is right, which means both ARI and non-ARI device >>>> have the upstream port(root port or downstream port), could the existence of >>>> upstream port be the judgment condition? >>> >>> This tells us whether we are behind a port that >>> can address devices in slot != 0. >>> >>> >> >> Seems I find something, according to spec: Endpoints are classified as >> either legacy, PCI Express, or Root Complex Integrated Endpoints. I think >> this is also what you means in comment "As there are several types of these" >> And "we are behind a port" means the device is not a Root Complex >> Integrated, only the other two types can be behind a port. >> >> Am I right about this? > > No, device can be a bridge itself. Ah yes, you are saying a PCIe-->PCI(PCI-X) bridge, right? > It's simple: root and downstream > ports only have 1 slot (and it's a physical one) so you know there's > always 1 device there. It could have multiple functions. > Yes, I am aware. It seems there is no big and obvious error about other understandings in last mail:) I just want to get myself totally understood about ARI and your implementation before using your code. Thank you very much for your time and patience:) And the v6 is on the way -- Yours Sincerely, Cao Jin