diff for duplicates of <563614A3.6060805@gmail.com> diff --git a/a/1.txt b/N1/1.txt index f996c88..2444e5a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,11 +3,11 @@ Hi, On 30/10/15 08:33, Chen-Yu Tsai wrote: > Hi, > -> On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske <jenskuske@gmail.com> wrote: +> On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: >> The Allwinner H3 is a home entertainment system oriented SoC with >> four Cortex-A7 cores and a Mali-400MP2 GPU. >> ->> Signed-off-by: Jens Kuske <jenskuske@gmail.com> +>> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> >> --- >> arch/arm/boot/dts/sun8i-h3.dtsi | 482 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 482 insertions(+) @@ -20,7 +20,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >> @@ -0,0 +1,482 @@ >> +/* ->> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> +>> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual @@ -73,25 +73,25 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + #address-cells = <1>; >> + #size-cells = <0>; >> + ->> + cpu at 0 { +>> + cpu@0 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <0>; >> + }; >> + ->> + cpu at 1 { +>> + cpu@1 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <1>; >> + }; >> + ->> + cpu at 2 { +>> + cpu@2 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <2>; >> + }; >> + ->> + cpu at 3 { +>> + cpu@3 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <3>; @@ -131,7 +131,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "osc32k"; >> + }; >> + ->> + pll1: clk at 01c20000 { +>> + pll1: clk@01c20000 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-a23-pll1-clk"; >> + reg = <0x01c20000 0x4>; @@ -147,7 +147,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "pll5"; >> + }; >> + ->> + pll6: clk at 01c20028 { +>> + pll6: clk@01c20028 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun6i-a31-pll6-clk"; >> + reg = <0x01c20028 0x4>; @@ -159,7 +159,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: > >> + }; >> + ->> + pll8: clk at 01c20044 { +>> + pll8: clk@01c20044 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun6i-a31-pll6-clk"; >> + reg = <0x01c20044 0x4>; @@ -167,7 +167,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "pll8", "pll8x2"; >> + }; >> + ->> + cpu: cpu_clk at 01c20050 { +>> + cpu: cpu_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-cpu-clk"; >> + reg = <0x01c20050 0x4>; @@ -175,7 +175,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "cpu"; >> + }; >> + ->> + axi: axi_clk at 01c20050 { +>> + axi: axi_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-axi-clk"; >> + reg = <0x01c20050 0x4>; @@ -183,7 +183,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "axi"; >> + }; >> + ->> + ahb1: ahb1_clk at 01c20054 { +>> + ahb1: ahb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun6i-a31-ahb1-clk"; >> + reg = <0x01c20054 0x4>; @@ -191,7 +191,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "ahb1"; >> + }; >> + ->> + ahb2: ahb2_clk at 01c2005c { +>> + ahb2: ahb2_clk@01c2005c { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-h3-ahb2-clk"; >> + reg = <0x01c2005c 0x4>; @@ -205,7 +205,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "ahb2"; >> + }; >> + ->> + apb1: apb1_clk at 01c20054 { +>> + apb1: apb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb0-clk"; >> + reg = <0x01c20054 0x4>; @@ -213,7 +213,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "apb1"; >> + }; >> + ->> + apb2: apb2_clk at 01c20058 { +>> + apb2: apb2_clk@01c20058 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb1-clk"; >> + reg = <0x01c20058 0x4>; @@ -221,7 +221,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "apb2"; >> + }; >> + ->> + bus_gates: clk at 01c20060 { +>> + bus_gates: clk@01c20060 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-bus-gates-clk"; >> + reg = <0x01c20060 0x14>; @@ -283,7 +283,7 @@ sent had issues somewhere... > >> + }; >> + ->> + mmc0_clk: clk at 01c20088 { +>> + mmc0_clk: clk@01c20088 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20088 0x4>; @@ -293,7 +293,7 @@ sent had issues somewhere... >> + "mmc0_sample"; >> + }; >> + ->> + mmc1_clk: clk at 01c2008c { +>> + mmc1_clk: clk@01c2008c { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c2008c 0x4>; @@ -303,7 +303,7 @@ sent had issues somewhere... >> + "mmc1_sample"; >> + }; >> + ->> + mmc2_clk: clk at 01c20090 { +>> + mmc2_clk: clk@01c20090 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20090 0x4>; @@ -313,7 +313,7 @@ sent had issues somewhere... >> + "mmc2_sample"; >> + }; >> + ->> + mbus_clk: clk at 01c2015c { +>> + mbus_clk: clk@01c2015c { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-a23-mbus-clk"; >> + reg = <0x01c2015c 0x4>; @@ -328,7 +328,7 @@ sent had issues somewhere... >> + #size-cells = <1>; >> + ranges; >> + ->> + dma: dma-controller at 01c02000 { +>> + dma: dma-controller@01c02000 { >> + compatible = "allwinner,sun8i-h3-dma"; >> + reg = <0x01c02000 0x1000>; >> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -337,7 +337,7 @@ sent had issues somewhere... >> + #dma-cells = <1>; >> + }; >> + ->> + mmc0: mmc at 01c0f000 { +>> + mmc0: mmc@01c0f000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c0f000 0x1000>; >> + clocks = <&bus_gates 8>, @@ -356,7 +356,7 @@ sent had issues somewhere... >> + #size-cells = <0>; >> + }; >> + ->> + mmc1: mmc at 01c10000 { +>> + mmc1: mmc@01c10000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c10000 0x1000>; >> + clocks = <&bus_gates 9>, @@ -375,7 +375,7 @@ sent had issues somewhere... >> + #size-cells = <0>; >> + }; >> + ->> + mmc2: mmc at 01c11000 { +>> + mmc2: mmc@01c11000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c11000 0x1000>; >> + clocks = <&bus_gates 10>, @@ -394,7 +394,7 @@ sent had issues somewhere... >> + #size-cells = <0>; >> + }; >> + ->> + pio: pinctrl at 01c20800 { +>> + pio: pinctrl@01c20800 { >> + compatible = "allwinner,sun8i-h3-pinctrl"; >> + reg = <0x01c20800 0x400>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -405,14 +405,14 @@ sent had issues somewhere... >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + ->> + uart0_pins_a: uart0 at 0 { +>> + uart0_pins_a: uart0@0 { >> + allwinner,pins = "PA4", "PA5"; >> + allwinner,function = "uart0"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + mmc0_pins_a: mmc0 at 0 { +>> + mmc0_pins_a: mmc0@0 { >> + allwinner,pins = "PF0", "PF1", "PF2", "PF3", >> + "PF4", "PF5"; >> + allwinner,function = "mmc0"; @@ -420,7 +420,7 @@ sent had issues somewhere... >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + mmc0_cd_pin: mmc0_cd_pin at 0 { +>> + mmc0_cd_pin: mmc0_cd_pin@0 { >> + allwinner,pins = "PF6"; >> + allwinner,function = "gpio_in"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -438,7 +438,7 @@ Jens >> + ->> + mmc1_pins_a: mmc1 at 0 { +>> + mmc1_pins_a: mmc1@0 { >> + allwinner,pins = "PG0", "PG1", "PG2", "PG3", >> + "PG4", "PG5"; >> + allwinner,function = "mmc1"; @@ -447,13 +447,13 @@ Jens >> + }; >> + }; >> + ->> + bus_rst: reset at 01c202c0 { +>> + bus_rst: reset@01c202c0 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun8i-h3-bus-reset"; >> + reg = <0x01c202c0 0x1c>; >> + }; >> + ->> + timer at 01c20c00 { +>> + timer@01c20c00 { >> + compatible = "allwinner,sun4i-a10-timer"; >> + reg = <0x01c20c00 0xa0>; >> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -461,13 +461,13 @@ Jens >> + clocks = <&osc24M>; >> + }; >> + ->> + wdt0: watchdog at 01c20ca0 { +>> + wdt0: watchdog@01c20ca0 { >> + compatible = "allwinner,sun6i-a31-wdt"; >> + reg = <0x01c20ca0 0x20>; >> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + ->> + uart0: serial at 01c28000 { +>> + uart0: serial@01c28000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28000 0x400>; >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -491,7 +491,7 @@ Jens >> + status = "disabled"; >> + }; >> + ->> + uart1: serial at 01c28400 { +>> + uart1: serial@01c28400 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28400 0x400>; >> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -504,7 +504,7 @@ Jens >> + status = "disabled"; >> + }; >> + ->> + uart2: serial at 01c28800 { +>> + uart2: serial@01c28800 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28800 0x400>; >> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -517,7 +517,7 @@ Jens >> + status = "disabled"; >> + }; >> + ->> + uart3: serial at 01c28c00 { +>> + uart3: serial@01c28c00 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28c00 0x400>; >> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -530,7 +530,7 @@ Jens >> + status = "disabled"; >> + }; >> + ->> + gic: interrupt-controller at 01c81000 { +>> + gic: interrupt-controller@01c81000 { >> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; >> + reg = <0x01c81000 0x1000>, >> + <0x01c82000 0x1000>, @@ -541,7 +541,7 @@ Jens >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> + }; >> + ->> + rtc: rtc at 01f00000 { +>> + rtc: rtc@01f00000 { >> + compatible = "allwinner,sun6i-a31-rtc"; >> + reg = <0x01f00000 0x54>; >> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, diff --git a/a/content_digest b/N1/content_digest index 5ee1242..9bba629 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,23 @@ "ref\01445964626-6484-1-git-send-email-jenskuske@gmail.com\0" "ref\01445964626-6484-6-git-send-email-jenskuske@gmail.com\0" "ref\0CAGb2v64NZMw0vNvVtepthUMox5TDy07gTBAWZqf8GAq6TrMpOg@mail.gmail.com\0" - "From\0jenskuske@gmail.com (Jens Kuske)\0" - "Subject\0[PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" + "ref\0CAGb2v64NZMw0vNvVtepthUMox5TDy07gTBAWZqf8GAq6TrMpOg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" + "From\0Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Subject\0Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" "Date\0Sun, 1 Nov 2015 14:33:23 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>\0" + "Cc\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>" + Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> + " Emilio L\303\263pez <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>" + Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> + devicetree <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-arm-kernel <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + linux-kernel <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + " linux-sunxi <linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>\0" "\00:1\0" "b\0" "Hi,\n" @@ -12,11 +25,11 @@ "On 30/10/15 08:33, Chen-Yu Tsai wrote:\n" "> Hi,\n" "> \n" - "> On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske <jenskuske@gmail.com> wrote:\n" + "> On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:\n" ">> The Allwinner H3 is a home entertainment system oriented SoC with\n" ">> four Cortex-A7 cores and a Mali-400MP2 GPU.\n" ">>\n" - ">> Signed-off-by: Jens Kuske <jenskuske@gmail.com>\n" + ">> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" ">> ---\n" ">> arch/arm/boot/dts/sun8i-h3.dtsi | 482 ++++++++++++++++++++++++++++++++++++++++\n" ">> 1 file changed, 482 insertions(+)\n" @@ -29,7 +42,7 @@ ">> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi\n" ">> @@ -0,0 +1,482 @@\n" ">> +/*\n" - ">> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>\n" + ">> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" ">> + *\n" ">> + * This file is dual-licensed: you can use it either under the terms\n" ">> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -82,25 +95,25 @@ ">> + #address-cells = <1>;\n" ">> + #size-cells = <0>;\n" ">> +\n" - ">> + cpu at 0 {\n" + ">> + cpu@0 {\n" ">> + compatible = \"arm,cortex-a7\";\n" ">> + device_type = \"cpu\";\n" ">> + reg = <0>;\n" ">> + };\n" ">> +\n" - ">> + cpu at 1 {\n" + ">> + cpu@1 {\n" ">> + compatible = \"arm,cortex-a7\";\n" ">> + device_type = \"cpu\";\n" ">> + reg = <1>;\n" ">> + };\n" ">> +\n" - ">> + cpu at 2 {\n" + ">> + cpu@2 {\n" ">> + compatible = \"arm,cortex-a7\";\n" ">> + device_type = \"cpu\";\n" ">> + reg = <2>;\n" ">> + };\n" ">> +\n" - ">> + cpu at 3 {\n" + ">> + cpu@3 {\n" ">> + compatible = \"arm,cortex-a7\";\n" ">> + device_type = \"cpu\";\n" ">> + reg = <3>;\n" @@ -140,7 +153,7 @@ ">> + clock-output-names = \"osc32k\";\n" ">> + };\n" ">> +\n" - ">> + pll1: clk at 01c20000 {\n" + ">> + pll1: clk@01c20000 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun8i-a23-pll1-clk\";\n" ">> + reg = <0x01c20000 0x4>;\n" @@ -156,7 +169,7 @@ ">> + clock-output-names = \"pll5\";\n" ">> + };\n" ">> +\n" - ">> + pll6: clk at 01c20028 {\n" + ">> + pll6: clk@01c20028 {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun6i-a31-pll6-clk\";\n" ">> + reg = <0x01c20028 0x4>;\n" @@ -168,7 +181,7 @@ "> \n" ">> + };\n" ">> +\n" - ">> + pll8: clk at 01c20044 {\n" + ">> + pll8: clk@01c20044 {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun6i-a31-pll6-clk\";\n" ">> + reg = <0x01c20044 0x4>;\n" @@ -176,7 +189,7 @@ ">> + clock-output-names = \"pll8\", \"pll8x2\";\n" ">> + };\n" ">> +\n" - ">> + cpu: cpu_clk at 01c20050 {\n" + ">> + cpu: cpu_clk@01c20050 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun4i-a10-cpu-clk\";\n" ">> + reg = <0x01c20050 0x4>;\n" @@ -184,7 +197,7 @@ ">> + clock-output-names = \"cpu\";\n" ">> + };\n" ">> +\n" - ">> + axi: axi_clk at 01c20050 {\n" + ">> + axi: axi_clk@01c20050 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun4i-a10-axi-clk\";\n" ">> + reg = <0x01c20050 0x4>;\n" @@ -192,7 +205,7 @@ ">> + clock-output-names = \"axi\";\n" ">> + };\n" ">> +\n" - ">> + ahb1: ahb1_clk at 01c20054 {\n" + ">> + ahb1: ahb1_clk@01c20054 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" ">> + reg = <0x01c20054 0x4>;\n" @@ -200,7 +213,7 @@ ">> + clock-output-names = \"ahb1\";\n" ">> + };\n" ">> +\n" - ">> + ahb2: ahb2_clk at 01c2005c {\n" + ">> + ahb2: ahb2_clk@01c2005c {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" ">> + reg = <0x01c2005c 0x4>;\n" @@ -214,7 +227,7 @@ ">> + clock-output-names = \"ahb2\";\n" ">> + };\n" ">> +\n" - ">> + apb1: apb1_clk at 01c20054 {\n" + ">> + apb1: apb1_clk@01c20054 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun4i-a10-apb0-clk\";\n" ">> + reg = <0x01c20054 0x4>;\n" @@ -222,7 +235,7 @@ ">> + clock-output-names = \"apb1\";\n" ">> + };\n" ">> +\n" - ">> + apb2: apb2_clk at 01c20058 {\n" + ">> + apb2: apb2_clk@01c20058 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun4i-a10-apb1-clk\";\n" ">> + reg = <0x01c20058 0x4>;\n" @@ -230,7 +243,7 @@ ">> + clock-output-names = \"apb2\";\n" ">> + };\n" ">> +\n" - ">> + bus_gates: clk at 01c20060 {\n" + ">> + bus_gates: clk@01c20060 {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun8i-h3-bus-gates-clk\";\n" ">> + reg = <0x01c20060 0x14>;\n" @@ -292,7 +305,7 @@ "> \n" ">> + };\n" ">> +\n" - ">> + mmc0_clk: clk at 01c20088 {\n" + ">> + mmc0_clk: clk@01c20088 {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> + reg = <0x01c20088 0x4>;\n" @@ -302,7 +315,7 @@ ">> + \"mmc0_sample\";\n" ">> + };\n" ">> +\n" - ">> + mmc1_clk: clk at 01c2008c {\n" + ">> + mmc1_clk: clk@01c2008c {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> + reg = <0x01c2008c 0x4>;\n" @@ -312,7 +325,7 @@ ">> + \"mmc1_sample\";\n" ">> + };\n" ">> +\n" - ">> + mmc2_clk: clk at 01c20090 {\n" + ">> + mmc2_clk: clk@01c20090 {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> + reg = <0x01c20090 0x4>;\n" @@ -322,7 +335,7 @@ ">> + \"mmc2_sample\";\n" ">> + };\n" ">> +\n" - ">> + mbus_clk: clk at 01c2015c {\n" + ">> + mbus_clk: clk@01c2015c {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun8i-a23-mbus-clk\";\n" ">> + reg = <0x01c2015c 0x4>;\n" @@ -337,7 +350,7 @@ ">> + #size-cells = <1>;\n" ">> + ranges;\n" ">> +\n" - ">> + dma: dma-controller at 01c02000 {\n" + ">> + dma: dma-controller@01c02000 {\n" ">> + compatible = \"allwinner,sun8i-h3-dma\";\n" ">> + reg = <0x01c02000 0x1000>;\n" ">> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -346,7 +359,7 @@ ">> + #dma-cells = <1>;\n" ">> + };\n" ">> +\n" - ">> + mmc0: mmc at 01c0f000 {\n" + ">> + mmc0: mmc@01c0f000 {\n" ">> + compatible = \"allwinner,sun5i-a13-mmc\";\n" ">> + reg = <0x01c0f000 0x1000>;\n" ">> + clocks = <&bus_gates 8>,\n" @@ -365,7 +378,7 @@ ">> + #size-cells = <0>;\n" ">> + };\n" ">> +\n" - ">> + mmc1: mmc at 01c10000 {\n" + ">> + mmc1: mmc@01c10000 {\n" ">> + compatible = \"allwinner,sun5i-a13-mmc\";\n" ">> + reg = <0x01c10000 0x1000>;\n" ">> + clocks = <&bus_gates 9>,\n" @@ -384,7 +397,7 @@ ">> + #size-cells = <0>;\n" ">> + };\n" ">> +\n" - ">> + mmc2: mmc at 01c11000 {\n" + ">> + mmc2: mmc@01c11000 {\n" ">> + compatible = \"allwinner,sun5i-a13-mmc\";\n" ">> + reg = <0x01c11000 0x1000>;\n" ">> + clocks = <&bus_gates 10>,\n" @@ -403,7 +416,7 @@ ">> + #size-cells = <0>;\n" ">> + };\n" ">> +\n" - ">> + pio: pinctrl at 01c20800 {\n" + ">> + pio: pinctrl@01c20800 {\n" ">> + compatible = \"allwinner,sun8i-h3-pinctrl\";\n" ">> + reg = <0x01c20800 0x400>;\n" ">> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -414,14 +427,14 @@ ">> + interrupt-controller;\n" ">> + #interrupt-cells = <2>;\n" ">> +\n" - ">> + uart0_pins_a: uart0 at 0 {\n" + ">> + uart0_pins_a: uart0@0 {\n" ">> + allwinner,pins = \"PA4\", \"PA5\";\n" ">> + allwinner,function = \"uart0\";\n" ">> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> + };\n" ">> +\n" - ">> + mmc0_pins_a: mmc0 at 0 {\n" + ">> + mmc0_pins_a: mmc0@0 {\n" ">> + allwinner,pins = \"PF0\", \"PF1\", \"PF2\", \"PF3\",\n" ">> + \"PF4\", \"PF5\";\n" ">> + allwinner,function = \"mmc0\";\n" @@ -429,7 +442,7 @@ ">> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> + };\n" ">> +\n" - ">> + mmc0_cd_pin: mmc0_cd_pin at 0 {\n" + ">> + mmc0_cd_pin: mmc0_cd_pin@0 {\n" ">> + allwinner,pins = \"PF6\";\n" ">> + allwinner,function = \"gpio_in\";\n" ">> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -447,7 +460,7 @@ "\n" "\n" ">> +\n" - ">> + mmc1_pins_a: mmc1 at 0 {\n" + ">> + mmc1_pins_a: mmc1@0 {\n" ">> + allwinner,pins = \"PG0\", \"PG1\", \"PG2\", \"PG3\",\n" ">> + \"PG4\", \"PG5\";\n" ">> + allwinner,function = \"mmc1\";\n" @@ -456,13 +469,13 @@ ">> + };\n" ">> + };\n" ">> +\n" - ">> + bus_rst: reset at 01c202c0 {\n" + ">> + bus_rst: reset@01c202c0 {\n" ">> + #reset-cells = <1>;\n" ">> + compatible = \"allwinner,sun8i-h3-bus-reset\";\n" ">> + reg = <0x01c202c0 0x1c>;\n" ">> + };\n" ">> +\n" - ">> + timer at 01c20c00 {\n" + ">> + timer@01c20c00 {\n" ">> + compatible = \"allwinner,sun4i-a10-timer\";\n" ">> + reg = <0x01c20c00 0xa0>;\n" ">> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -470,13 +483,13 @@ ">> + clocks = <&osc24M>;\n" ">> + };\n" ">> +\n" - ">> + wdt0: watchdog at 01c20ca0 {\n" + ">> + wdt0: watchdog@01c20ca0 {\n" ">> + compatible = \"allwinner,sun6i-a31-wdt\";\n" ">> + reg = <0x01c20ca0 0x20>;\n" ">> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n" ">> + };\n" ">> +\n" - ">> + uart0: serial at 01c28000 {\n" + ">> + uart0: serial@01c28000 {\n" ">> + compatible = \"snps,dw-apb-uart\";\n" ">> + reg = <0x01c28000 0x400>;\n" ">> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -500,7 +513,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart1: serial at 01c28400 {\n" + ">> + uart1: serial@01c28400 {\n" ">> + compatible = \"snps,dw-apb-uart\";\n" ">> + reg = <0x01c28400 0x400>;\n" ">> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -513,7 +526,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart2: serial at 01c28800 {\n" + ">> + uart2: serial@01c28800 {\n" ">> + compatible = \"snps,dw-apb-uart\";\n" ">> + reg = <0x01c28800 0x400>;\n" ">> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -526,7 +539,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart3: serial at 01c28c00 {\n" + ">> + uart3: serial@01c28c00 {\n" ">> + compatible = \"snps,dw-apb-uart\";\n" ">> + reg = <0x01c28c00 0x400>;\n" ">> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -539,7 +552,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + gic: interrupt-controller at 01c81000 {\n" + ">> + gic: interrupt-controller@01c81000 {\n" ">> + compatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n" ">> + reg = <0x01c81000 0x1000>,\n" ">> + <0x01c82000 0x1000>,\n" @@ -550,7 +563,7 @@ ">> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" ">> + };\n" ">> +\n" - ">> + rtc: rtc at 01f00000 {\n" + ">> + rtc: rtc@01f00000 {\n" ">> + compatible = \"allwinner,sun6i-a31-rtc\";\n" ">> + reg = <0x01f00000 0x54>;\n" ">> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -563,4 +576,4 @@ ">>\n" > -f6b871e137181035d685e7f90739d093b5ae508e90988dc78f16434922a39de5 +4cb4b68eab135261ef7b32feef6e6359d83386e29a85404577907cec5f022324
diff --git a/a/1.txt b/N2/1.txt index f996c88..5d915f9 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -73,25 +73,25 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + #address-cells = <1>; >> + #size-cells = <0>; >> + ->> + cpu at 0 { +>> + cpu@0 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <0>; >> + }; >> + ->> + cpu at 1 { +>> + cpu@1 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <1>; >> + }; >> + ->> + cpu at 2 { +>> + cpu@2 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <2>; >> + }; >> + ->> + cpu at 3 { +>> + cpu@3 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <3>; @@ -131,7 +131,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "osc32k"; >> + }; >> + ->> + pll1: clk at 01c20000 { +>> + pll1: clk@01c20000 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-a23-pll1-clk"; >> + reg = <0x01c20000 0x4>; @@ -147,7 +147,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "pll5"; >> + }; >> + ->> + pll6: clk at 01c20028 { +>> + pll6: clk@01c20028 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun6i-a31-pll6-clk"; >> + reg = <0x01c20028 0x4>; @@ -159,7 +159,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: > >> + }; >> + ->> + pll8: clk at 01c20044 { +>> + pll8: clk@01c20044 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun6i-a31-pll6-clk"; >> + reg = <0x01c20044 0x4>; @@ -167,7 +167,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "pll8", "pll8x2"; >> + }; >> + ->> + cpu: cpu_clk at 01c20050 { +>> + cpu: cpu_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-cpu-clk"; >> + reg = <0x01c20050 0x4>; @@ -175,7 +175,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "cpu"; >> + }; >> + ->> + axi: axi_clk at 01c20050 { +>> + axi: axi_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-axi-clk"; >> + reg = <0x01c20050 0x4>; @@ -183,7 +183,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "axi"; >> + }; >> + ->> + ahb1: ahb1_clk at 01c20054 { +>> + ahb1: ahb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun6i-a31-ahb1-clk"; >> + reg = <0x01c20054 0x4>; @@ -191,7 +191,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "ahb1"; >> + }; >> + ->> + ahb2: ahb2_clk at 01c2005c { +>> + ahb2: ahb2_clk@01c2005c { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-h3-ahb2-clk"; >> + reg = <0x01c2005c 0x4>; @@ -205,7 +205,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "ahb2"; >> + }; >> + ->> + apb1: apb1_clk at 01c20054 { +>> + apb1: apb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb0-clk"; >> + reg = <0x01c20054 0x4>; @@ -213,7 +213,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "apb1"; >> + }; >> + ->> + apb2: apb2_clk at 01c20058 { +>> + apb2: apb2_clk@01c20058 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb1-clk"; >> + reg = <0x01c20058 0x4>; @@ -221,7 +221,7 @@ On 30/10/15 08:33, Chen-Yu Tsai wrote: >> + clock-output-names = "apb2"; >> + }; >> + ->> + bus_gates: clk at 01c20060 { +>> + bus_gates: clk@01c20060 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun8i-h3-bus-gates-clk"; >> + reg = <0x01c20060 0x14>; @@ -283,7 +283,7 @@ sent had issues somewhere... > >> + }; >> + ->> + mmc0_clk: clk at 01c20088 { +>> + mmc0_clk: clk@01c20088 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20088 0x4>; @@ -293,7 +293,7 @@ sent had issues somewhere... >> + "mmc0_sample"; >> + }; >> + ->> + mmc1_clk: clk at 01c2008c { +>> + mmc1_clk: clk@01c2008c { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c2008c 0x4>; @@ -303,7 +303,7 @@ sent had issues somewhere... >> + "mmc1_sample"; >> + }; >> + ->> + mmc2_clk: clk at 01c20090 { +>> + mmc2_clk: clk@01c20090 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20090 0x4>; @@ -313,7 +313,7 @@ sent had issues somewhere... >> + "mmc2_sample"; >> + }; >> + ->> + mbus_clk: clk at 01c2015c { +>> + mbus_clk: clk@01c2015c { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-a23-mbus-clk"; >> + reg = <0x01c2015c 0x4>; @@ -328,7 +328,7 @@ sent had issues somewhere... >> + #size-cells = <1>; >> + ranges; >> + ->> + dma: dma-controller at 01c02000 { +>> + dma: dma-controller@01c02000 { >> + compatible = "allwinner,sun8i-h3-dma"; >> + reg = <0x01c02000 0x1000>; >> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -337,7 +337,7 @@ sent had issues somewhere... >> + #dma-cells = <1>; >> + }; >> + ->> + mmc0: mmc at 01c0f000 { +>> + mmc0: mmc@01c0f000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c0f000 0x1000>; >> + clocks = <&bus_gates 8>, @@ -356,7 +356,7 @@ sent had issues somewhere... >> + #size-cells = <0>; >> + }; >> + ->> + mmc1: mmc at 01c10000 { +>> + mmc1: mmc@01c10000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c10000 0x1000>; >> + clocks = <&bus_gates 9>, @@ -375,7 +375,7 @@ sent had issues somewhere... >> + #size-cells = <0>; >> + }; >> + ->> + mmc2: mmc at 01c11000 { +>> + mmc2: mmc@01c11000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c11000 0x1000>; >> + clocks = <&bus_gates 10>, @@ -394,7 +394,7 @@ sent had issues somewhere... >> + #size-cells = <0>; >> + }; >> + ->> + pio: pinctrl at 01c20800 { +>> + pio: pinctrl@01c20800 { >> + compatible = "allwinner,sun8i-h3-pinctrl"; >> + reg = <0x01c20800 0x400>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -405,14 +405,14 @@ sent had issues somewhere... >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + ->> + uart0_pins_a: uart0 at 0 { +>> + uart0_pins_a: uart0@0 { >> + allwinner,pins = "PA4", "PA5"; >> + allwinner,function = "uart0"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + mmc0_pins_a: mmc0 at 0 { +>> + mmc0_pins_a: mmc0@0 { >> + allwinner,pins = "PF0", "PF1", "PF2", "PF3", >> + "PF4", "PF5"; >> + allwinner,function = "mmc0"; @@ -420,7 +420,7 @@ sent had issues somewhere... >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + mmc0_cd_pin: mmc0_cd_pin at 0 { +>> + mmc0_cd_pin: mmc0_cd_pin@0 { >> + allwinner,pins = "PF6"; >> + allwinner,function = "gpio_in"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -438,7 +438,7 @@ Jens >> + ->> + mmc1_pins_a: mmc1 at 0 { +>> + mmc1_pins_a: mmc1@0 { >> + allwinner,pins = "PG0", "PG1", "PG2", "PG3", >> + "PG4", "PG5"; >> + allwinner,function = "mmc1"; @@ -447,13 +447,13 @@ Jens >> + }; >> + }; >> + ->> + bus_rst: reset at 01c202c0 { +>> + bus_rst: reset@01c202c0 { >> + #reset-cells = <1>; >> + compatible = "allwinner,sun8i-h3-bus-reset"; >> + reg = <0x01c202c0 0x1c>; >> + }; >> + ->> + timer at 01c20c00 { +>> + timer@01c20c00 { >> + compatible = "allwinner,sun4i-a10-timer"; >> + reg = <0x01c20c00 0xa0>; >> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, @@ -461,13 +461,13 @@ Jens >> + clocks = <&osc24M>; >> + }; >> + ->> + wdt0: watchdog at 01c20ca0 { +>> + wdt0: watchdog@01c20ca0 { >> + compatible = "allwinner,sun6i-a31-wdt"; >> + reg = <0x01c20ca0 0x20>; >> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + ->> + uart0: serial at 01c28000 { +>> + uart0: serial@01c28000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28000 0x400>; >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -491,7 +491,7 @@ Jens >> + status = "disabled"; >> + }; >> + ->> + uart1: serial at 01c28400 { +>> + uart1: serial@01c28400 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28400 0x400>; >> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -504,7 +504,7 @@ Jens >> + status = "disabled"; >> + }; >> + ->> + uart2: serial at 01c28800 { +>> + uart2: serial@01c28800 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28800 0x400>; >> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -517,7 +517,7 @@ Jens >> + status = "disabled"; >> + }; >> + ->> + uart3: serial at 01c28c00 { +>> + uart3: serial@01c28c00 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x01c28c00 0x400>; >> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -530,7 +530,7 @@ Jens >> + status = "disabled"; >> + }; >> + ->> + gic: interrupt-controller at 01c81000 { +>> + gic: interrupt-controller@01c81000 { >> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; >> + reg = <0x01c81000 0x1000>, >> + <0x01c82000 0x1000>, @@ -541,7 +541,7 @@ Jens >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> + }; >> + ->> + rtc: rtc at 01f00000 { +>> + rtc: rtc@01f00000 { >> + compatible = "allwinner,sun6i-a31-rtc"; >> + reg = <0x01f00000 0x54>; >> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, diff --git a/a/content_digest b/N2/content_digest index 5ee1242..755b62a 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,10 +1,22 @@ "ref\01445964626-6484-1-git-send-email-jenskuske@gmail.com\0" "ref\01445964626-6484-6-git-send-email-jenskuske@gmail.com\0" "ref\0CAGb2v64NZMw0vNvVtepthUMox5TDy07gTBAWZqf8GAq6TrMpOg@mail.gmail.com\0" - "From\0jenskuske@gmail.com (Jens Kuske)\0" - "Subject\0[PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" + "From\0Jens Kuske <jenskuske@gmail.com>\0" + "Subject\0Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" "Date\0Sun, 1 Nov 2015 14:33:23 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Chen-Yu Tsai <wens@csie.org>\0" + "Cc\0Maxime Ripard <maxime.ripard@free-electrons.com>" + Michael Turquette <mturquette@baylibre.com> + Linus Walleij <linus.walleij@linaro.org> + Rob Herring <robh+dt@kernel.org> + Philipp Zabel <p.zabel@pengutronix.de> + " Emilio L\303\263pez <emilio@elopez.com.ar>" + Vishnu Patekar <vishnupatekar0510@gmail.com> + Hans de Goede <hdegoede@redhat.com> + devicetree <devicetree@vger.kernel.org> + linux-arm-kernel <linux-arm-kernel@lists.infradead.org> + linux-kernel <linux-kernel@vger.kernel.org> + " linux-sunxi <linux-sunxi@googlegroups.com>\0" "\00:1\0" "b\0" "Hi,\n" @@ -82,25 +94,25 @@ ">> + #address-cells = <1>;\n" ">> + #size-cells = <0>;\n" ">> +\n" - ">> + cpu at 0 {\n" + ">> + cpu@0 {\n" ">> + compatible = \"arm,cortex-a7\";\n" ">> + device_type = \"cpu\";\n" ">> + reg = <0>;\n" ">> + };\n" ">> +\n" - ">> + cpu at 1 {\n" + ">> + cpu@1 {\n" ">> + compatible = \"arm,cortex-a7\";\n" ">> + device_type = \"cpu\";\n" ">> + reg = <1>;\n" ">> + };\n" ">> +\n" - ">> + cpu at 2 {\n" + ">> + cpu@2 {\n" ">> + compatible = \"arm,cortex-a7\";\n" ">> + device_type = \"cpu\";\n" ">> + reg = <2>;\n" ">> + };\n" ">> +\n" - ">> + cpu at 3 {\n" + ">> + cpu@3 {\n" ">> + compatible = \"arm,cortex-a7\";\n" ">> + device_type = \"cpu\";\n" ">> + reg = <3>;\n" @@ -140,7 +152,7 @@ ">> + clock-output-names = \"osc32k\";\n" ">> + };\n" ">> +\n" - ">> + pll1: clk at 01c20000 {\n" + ">> + pll1: clk@01c20000 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun8i-a23-pll1-clk\";\n" ">> + reg = <0x01c20000 0x4>;\n" @@ -156,7 +168,7 @@ ">> + clock-output-names = \"pll5\";\n" ">> + };\n" ">> +\n" - ">> + pll6: clk at 01c20028 {\n" + ">> + pll6: clk@01c20028 {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun6i-a31-pll6-clk\";\n" ">> + reg = <0x01c20028 0x4>;\n" @@ -168,7 +180,7 @@ "> \n" ">> + };\n" ">> +\n" - ">> + pll8: clk at 01c20044 {\n" + ">> + pll8: clk@01c20044 {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun6i-a31-pll6-clk\";\n" ">> + reg = <0x01c20044 0x4>;\n" @@ -176,7 +188,7 @@ ">> + clock-output-names = \"pll8\", \"pll8x2\";\n" ">> + };\n" ">> +\n" - ">> + cpu: cpu_clk at 01c20050 {\n" + ">> + cpu: cpu_clk@01c20050 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun4i-a10-cpu-clk\";\n" ">> + reg = <0x01c20050 0x4>;\n" @@ -184,7 +196,7 @@ ">> + clock-output-names = \"cpu\";\n" ">> + };\n" ">> +\n" - ">> + axi: axi_clk at 01c20050 {\n" + ">> + axi: axi_clk@01c20050 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun4i-a10-axi-clk\";\n" ">> + reg = <0x01c20050 0x4>;\n" @@ -192,7 +204,7 @@ ">> + clock-output-names = \"axi\";\n" ">> + };\n" ">> +\n" - ">> + ahb1: ahb1_clk at 01c20054 {\n" + ">> + ahb1: ahb1_clk@01c20054 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" ">> + reg = <0x01c20054 0x4>;\n" @@ -200,7 +212,7 @@ ">> + clock-output-names = \"ahb1\";\n" ">> + };\n" ">> +\n" - ">> + ahb2: ahb2_clk at 01c2005c {\n" + ">> + ahb2: ahb2_clk@01c2005c {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" ">> + reg = <0x01c2005c 0x4>;\n" @@ -214,7 +226,7 @@ ">> + clock-output-names = \"ahb2\";\n" ">> + };\n" ">> +\n" - ">> + apb1: apb1_clk at 01c20054 {\n" + ">> + apb1: apb1_clk@01c20054 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun4i-a10-apb0-clk\";\n" ">> + reg = <0x01c20054 0x4>;\n" @@ -222,7 +234,7 @@ ">> + clock-output-names = \"apb1\";\n" ">> + };\n" ">> +\n" - ">> + apb2: apb2_clk at 01c20058 {\n" + ">> + apb2: apb2_clk@01c20058 {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun4i-a10-apb1-clk\";\n" ">> + reg = <0x01c20058 0x4>;\n" @@ -230,7 +242,7 @@ ">> + clock-output-names = \"apb2\";\n" ">> + };\n" ">> +\n" - ">> + bus_gates: clk at 01c20060 {\n" + ">> + bus_gates: clk@01c20060 {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun8i-h3-bus-gates-clk\";\n" ">> + reg = <0x01c20060 0x14>;\n" @@ -292,7 +304,7 @@ "> \n" ">> + };\n" ">> +\n" - ">> + mmc0_clk: clk at 01c20088 {\n" + ">> + mmc0_clk: clk@01c20088 {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> + reg = <0x01c20088 0x4>;\n" @@ -302,7 +314,7 @@ ">> + \"mmc0_sample\";\n" ">> + };\n" ">> +\n" - ">> + mmc1_clk: clk at 01c2008c {\n" + ">> + mmc1_clk: clk@01c2008c {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> + reg = <0x01c2008c 0x4>;\n" @@ -312,7 +324,7 @@ ">> + \"mmc1_sample\";\n" ">> + };\n" ">> +\n" - ">> + mmc2_clk: clk at 01c20090 {\n" + ">> + mmc2_clk: clk@01c20090 {\n" ">> + #clock-cells = <1>;\n" ">> + compatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> + reg = <0x01c20090 0x4>;\n" @@ -322,7 +334,7 @@ ">> + \"mmc2_sample\";\n" ">> + };\n" ">> +\n" - ">> + mbus_clk: clk at 01c2015c {\n" + ">> + mbus_clk: clk@01c2015c {\n" ">> + #clock-cells = <0>;\n" ">> + compatible = \"allwinner,sun8i-a23-mbus-clk\";\n" ">> + reg = <0x01c2015c 0x4>;\n" @@ -337,7 +349,7 @@ ">> + #size-cells = <1>;\n" ">> + ranges;\n" ">> +\n" - ">> + dma: dma-controller at 01c02000 {\n" + ">> + dma: dma-controller@01c02000 {\n" ">> + compatible = \"allwinner,sun8i-h3-dma\";\n" ">> + reg = <0x01c02000 0x1000>;\n" ">> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -346,7 +358,7 @@ ">> + #dma-cells = <1>;\n" ">> + };\n" ">> +\n" - ">> + mmc0: mmc at 01c0f000 {\n" + ">> + mmc0: mmc@01c0f000 {\n" ">> + compatible = \"allwinner,sun5i-a13-mmc\";\n" ">> + reg = <0x01c0f000 0x1000>;\n" ">> + clocks = <&bus_gates 8>,\n" @@ -365,7 +377,7 @@ ">> + #size-cells = <0>;\n" ">> + };\n" ">> +\n" - ">> + mmc1: mmc at 01c10000 {\n" + ">> + mmc1: mmc@01c10000 {\n" ">> + compatible = \"allwinner,sun5i-a13-mmc\";\n" ">> + reg = <0x01c10000 0x1000>;\n" ">> + clocks = <&bus_gates 9>,\n" @@ -384,7 +396,7 @@ ">> + #size-cells = <0>;\n" ">> + };\n" ">> +\n" - ">> + mmc2: mmc at 01c11000 {\n" + ">> + mmc2: mmc@01c11000 {\n" ">> + compatible = \"allwinner,sun5i-a13-mmc\";\n" ">> + reg = <0x01c11000 0x1000>;\n" ">> + clocks = <&bus_gates 10>,\n" @@ -403,7 +415,7 @@ ">> + #size-cells = <0>;\n" ">> + };\n" ">> +\n" - ">> + pio: pinctrl at 01c20800 {\n" + ">> + pio: pinctrl@01c20800 {\n" ">> + compatible = \"allwinner,sun8i-h3-pinctrl\";\n" ">> + reg = <0x01c20800 0x400>;\n" ">> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -414,14 +426,14 @@ ">> + interrupt-controller;\n" ">> + #interrupt-cells = <2>;\n" ">> +\n" - ">> + uart0_pins_a: uart0 at 0 {\n" + ">> + uart0_pins_a: uart0@0 {\n" ">> + allwinner,pins = \"PA4\", \"PA5\";\n" ">> + allwinner,function = \"uart0\";\n" ">> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> + };\n" ">> +\n" - ">> + mmc0_pins_a: mmc0 at 0 {\n" + ">> + mmc0_pins_a: mmc0@0 {\n" ">> + allwinner,pins = \"PF0\", \"PF1\", \"PF2\", \"PF3\",\n" ">> + \"PF4\", \"PF5\";\n" ">> + allwinner,function = \"mmc0\";\n" @@ -429,7 +441,7 @@ ">> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> + };\n" ">> +\n" - ">> + mmc0_cd_pin: mmc0_cd_pin at 0 {\n" + ">> + mmc0_cd_pin: mmc0_cd_pin@0 {\n" ">> + allwinner,pins = \"PF6\";\n" ">> + allwinner,function = \"gpio_in\";\n" ">> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -447,7 +459,7 @@ "\n" "\n" ">> +\n" - ">> + mmc1_pins_a: mmc1 at 0 {\n" + ">> + mmc1_pins_a: mmc1@0 {\n" ">> + allwinner,pins = \"PG0\", \"PG1\", \"PG2\", \"PG3\",\n" ">> + \"PG4\", \"PG5\";\n" ">> + allwinner,function = \"mmc1\";\n" @@ -456,13 +468,13 @@ ">> + };\n" ">> + };\n" ">> +\n" - ">> + bus_rst: reset at 01c202c0 {\n" + ">> + bus_rst: reset@01c202c0 {\n" ">> + #reset-cells = <1>;\n" ">> + compatible = \"allwinner,sun8i-h3-bus-reset\";\n" ">> + reg = <0x01c202c0 0x1c>;\n" ">> + };\n" ">> +\n" - ">> + timer at 01c20c00 {\n" + ">> + timer@01c20c00 {\n" ">> + compatible = \"allwinner,sun4i-a10-timer\";\n" ">> + reg = <0x01c20c00 0xa0>;\n" ">> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -470,13 +482,13 @@ ">> + clocks = <&osc24M>;\n" ">> + };\n" ">> +\n" - ">> + wdt0: watchdog at 01c20ca0 {\n" + ">> + wdt0: watchdog@01c20ca0 {\n" ">> + compatible = \"allwinner,sun6i-a31-wdt\";\n" ">> + reg = <0x01c20ca0 0x20>;\n" ">> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;\n" ">> + };\n" ">> +\n" - ">> + uart0: serial at 01c28000 {\n" + ">> + uart0: serial@01c28000 {\n" ">> + compatible = \"snps,dw-apb-uart\";\n" ">> + reg = <0x01c28000 0x400>;\n" ">> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -500,7 +512,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart1: serial at 01c28400 {\n" + ">> + uart1: serial@01c28400 {\n" ">> + compatible = \"snps,dw-apb-uart\";\n" ">> + reg = <0x01c28400 0x400>;\n" ">> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -513,7 +525,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart2: serial at 01c28800 {\n" + ">> + uart2: serial@01c28800 {\n" ">> + compatible = \"snps,dw-apb-uart\";\n" ">> + reg = <0x01c28800 0x400>;\n" ">> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -526,7 +538,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + uart3: serial at 01c28c00 {\n" + ">> + uart3: serial@01c28c00 {\n" ">> + compatible = \"snps,dw-apb-uart\";\n" ">> + reg = <0x01c28c00 0x400>;\n" ">> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -539,7 +551,7 @@ ">> + status = \"disabled\";\n" ">> + };\n" ">> +\n" - ">> + gic: interrupt-controller at 01c81000 {\n" + ">> + gic: interrupt-controller@01c81000 {\n" ">> + compatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n" ">> + reg = <0x01c81000 0x1000>,\n" ">> + <0x01c82000 0x1000>,\n" @@ -550,7 +562,7 @@ ">> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" ">> + };\n" ">> +\n" - ">> + rtc: rtc at 01f00000 {\n" + ">> + rtc: rtc@01f00000 {\n" ">> + compatible = \"allwinner,sun6i-a31-rtc\";\n" ">> + reg = <0x01f00000 0x54>;\n" ">> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -563,4 +575,4 @@ ">>\n" > -f6b871e137181035d685e7f90739d093b5ae508e90988dc78f16434922a39de5 +1a94bc7c7205ecf8a3b709082b9ee02569f61707b4b8cf0c6d1f0275bcc7bc31
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