From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514
Date: Wed, 4 Nov 2015 10:46:13 -0800 [thread overview]
Message-ID: <563A5275.6020405@freescale.com> (raw)
In-Reply-To: <1445422497-29230-4-git-send-email-yao.yuan@freescale.com>
On 10/21/2015 03:14 AM, Yuan Yao wrote:
> Affects: DDR
> Description: Memory controller performance is not optimal with default
> internal target queue register values.
> Impact: Memory controller performance is not optimal.
> Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
>
>
Please rewrite the commit message to explain why and what this patch does, not
copy-n-paste from erratum document.
York
next prev parent reply other threads:[~2015-11-04 18:46 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-21 10:14 [U-Boot] [PATCH 1/5] arm: ls1021a: merge SoC specific code in a separate file Yuan Yao
2015-10-21 10:14 ` [U-Boot] [PATCH 2/5] arm: ls102xa: enable all the snoop signal for masters Yuan Yao
2015-10-21 10:14 ` [U-Boot] [PATCH 3/5] ls102xa: Enable snoop and DVM message requests Yuan Yao
2015-10-21 10:14 ` [U-Boot] [PATCH 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514 Yuan Yao
2015-11-04 18:46 ` York Sun [this message]
2015-10-21 10:14 ` [U-Boot] [PATCH 5/5] LS102XA:workaround:disable priorities within DDR Yuan Yao
2015-11-04 18:48 ` York Sun
2015-11-05 7:22 ` Yao Yuan
2015-11-04 8:51 ` [U-Boot] [PATCH 1/5] arm: ls1021a: merge SoC specific code in a separate file Huan Wang
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