From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Christian_K=c3=b6nig?= Date: Thu, 05 Nov 2015 10:43:19 +0000 Subject: Re: Mobility Radeon HD 4530/4570/545v: flicker in 1920x1080 Message-Id: <563B32C7.3080202@vodafone.de> List-Id: References: <20151031201344.GA30459@amd> <563522C5.1000206@amd.com> <20151031212259.GA6253@amd> <20151103220919.GA4824@amd> <20151103230329.GA4167@amd> <5639B580.1050409@vodafone.de> <20151104221000.GA3608@amd> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Alex Deucher , Pavel Machek Cc: "Deucher, Alexander" , "linux-fbdev@vger.kernel.org" , =?UTF-8?Q?Christian_K=c3=b6nig?= , Maling list - DRI developers , kernel list On 04.11.2015 23:13, Alex Deucher wrote: > On Wed, Nov 4, 2015 at 5:10 PM, Pavel Machek wrote: >> Hi! >> >>>>>>> index dac78ad..b86f06a 100644 >>>>>>> --- a/drivers/gpu/drm/radeon/atombios_crtc.c >>>>>>> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c >>>>>>> @@ -569,6 +569,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, >>>>>>> radeon_crtc->pll_flags = 0; >>>>>>> >>>>>>> if (ASIC_IS_AVIVO(rdev)) { >>>>>>> + radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; >>>>>>> + >>>>>>> if ((rdev->family = CHIP_RS600) || >>>>>>> (rdev->family = CHIP_RS690) || >>>>>>> (rdev->family = CHIP_RS740)) >>>>>>> >>>>>> Help.. maybe... it is tricky to tell. It definitely does _not_ fix the >>>>>> issue completely. >>>>> You could also try the old pll algorithm: >>>> I reverted the patch above, and switched to the old algorithm. >>>> >>>> The flicker is still there. (But maybe its less horrible, like with >>>> RADEON_PLL_PREFER_MINM_OVER_MAXP). >>> The flickering would vanish completely if that's the reason for the issue >>> you are seeing. >>> Try setting ref_div_min and ref_div_max to 2 in >>> radeon_compute_pll_avivo(). >> Ok, I did this, but no luck, still flickers. But the flicker only >> happens when something changes on screen, like dragging a big >> window. Is that consistent with wrong PLL timings? > Does it go away with radeon.dpm=0? Sounds more like either memory > reclocking happening outside of vblank, or underflow to the display > controllers. Sounds like my suspicion was right, that doesn't seem to be a PLL issue after all. Just to rule out the obvious your system works fine with windows and you don't have a extra long cable for the monitor or something like this? Regards, Christian. > > Alex > >> diff --git a/config.32 b/config.32 >> index 00e5dd2..4734158 100644 >> --- a/config.32 >> +++ b/config.32 >> @@ -1090,7 +1090,7 @@ CONFIG_DEVTMPFS_MOUNT=y >> CONFIG_PREVENT_FIRMWARE_BUILD=y >> CONFIG_FW_LOADER=y >> CONFIG_FIRMWARE_IN_KERNEL=y >> -CONFIG_EXTRA_FIRMWARE="radeon/R700_rlc.bin" >> +CONFIG_EXTRA_FIRMWARE="radeon/R700_rlc.bin radeon/RV710_smc.bin radeon/RV710_uvd.bin" >> CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware" >> # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set >> CONFIG_ALLOW_DEV_COREDUMP=y >> diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c >> index dac78ad..dcc4f4d 100644 >> --- a/drivers/gpu/drm/radeon/atombios_crtc.c >> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c >> @@ -569,6 +569,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, >> radeon_crtc->pll_flags = 0; >> >> if (ASIC_IS_AVIVO(rdev)) { >> + //radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; >> + >> if ((rdev->family = CHIP_RS600) || >> (rdev->family = CHIP_RS690) || >> (rdev->family = CHIP_RS740)) >> diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c >> index 6743174..bebaf4f 100644 >> --- a/drivers/gpu/drm/radeon/radeon_display.c >> +++ b/drivers/gpu/drm/radeon/radeon_display.c >> @@ -947,6 +947,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, >> fb_div_max = pll->max_feedback_div; >> >> if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { >> + printk("radeon: fractional divider\n"); >> fb_div_min *= 10; >> fb_div_max *= 10; >> } >> @@ -966,6 +967,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, >> else >> ref_div_max = pll->max_ref_div; >> >> + ref_div_min = 2; >> + ref_div_max = 2; >> + >> /* determine allowed post divider range */ >> if (pll->flags & RADEON_PLL_USE_POST_DIV) { >> post_div_min = pll->post_div; >> @@ -1020,6 +1024,8 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, >> diff = abs(target_clock - (pll->reference_freq * fb_div) / >> (ref_div * post_div)); >> >> + printk("post_div = %d, diff = %d\n", post_div, diff); >> + >> if (diff < diff_best || (diff = diff_best && >> !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { >> >> @@ -1028,6 +1034,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, >> } >> } >> post_div = post_div_best; >> + printk("Selected post_div = %d\n", post_div); >> >> /* get the feedback and reference divider for the optimal value */ >> avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, >> @@ -1062,7 +1069,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, >> *ref_div_p = ref_div; >> *post_div_p = post_div; >> >> - DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", >> + printk("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", >> freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, >> ref_div, post_div); >> } >> >> >>> But I'm not 100% convinced that this is actually a PLL problem, try to >>> compile the firmware it complains about into the kernel as well. >> Did that, too. >> >> Best regards, >> Pavel >> -- >> (english) http://www.livejournal.com/~pavelmachek >> (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Christian_K=c3=b6nig?= Subject: Re: Mobility Radeon HD 4530/4570/545v: flicker in 1920x1080 Date: Thu, 5 Nov 2015 11:43:19 +0100 Message-ID: <563B32C7.3080202@vodafone.de> References: <20151031201344.GA30459@amd> <563522C5.1000206@amd.com> <20151031212259.GA6253@amd> <20151103220919.GA4824@amd> <20151103230329.GA4167@amd> <5639B580.1050409@vodafone.de> <20151104221000.GA3608@amd> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: Received: from pegasos-out.vodafone.de (pegasos-out.vodafone.de [80.84.1.38]) by gabe.freedesktop.org (Postfix) with ESMTP id F03946E9F7 for ; Thu, 5 Nov 2015 02:43:40 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Alex Deucher , Pavel Machek Cc: "Deucher, Alexander" , "linux-fbdev@vger.kernel.org" , =?UTF-8?Q?Christian_K=c3=b6nig?= , Maling list - DRI developers , kernel list List-Id: dri-devel@lists.freedesktop.org T24gMDQuMTEuMjAxNSAyMzoxMywgQWxleCBEZXVjaGVyIHdyb3RlOgo+IE9uIFdlZCwgTm92IDQs IDIwMTUgYXQgNToxMCBQTSwgUGF2ZWwgTWFjaGVrIDxwYXZlbEB1Y3cuY3o+IHdyb3RlOgo+PiBI aSEKPj4KPj4+Pj4+PiBpbmRleCBkYWM3OGFkLi5iODZmMDZhIDEwMDY0NAo+Pj4+Pj4+IC0tLSBh L2RyaXZlcnMvZ3B1L2RybS9yYWRlb24vYXRvbWJpb3NfY3J0Yy5jCj4+Pj4+Pj4gKysrIGIvZHJp dmVycy9ncHUvZHJtL3JhZGVvbi9hdG9tYmlvc19jcnRjLmMKPj4+Pj4+PiBAQCAtNTY5LDYgKzU2 OSw4IEBAIHN0YXRpYyB1MzIgYXRvbWJpb3NfYWRqdXN0X3BsbChzdHJ1Y3QgZHJtX2NydGMgKmNy dGMsCj4+Pj4+Pj4gICAgICAgICAgcmFkZW9uX2NydGMtPnBsbF9mbGFncyA9IDA7Cj4+Pj4+Pj4K Pj4+Pj4+PiAgICAgICAgICBpZiAoQVNJQ19JU19BVklWTyhyZGV2KSkgewo+Pj4+Pj4+ICsgICAg ICAgICAgICAgICByYWRlb25fY3J0Yy0+cGxsX2ZsYWdzIHw9IFJBREVPTl9QTExfUFJFRkVSX01J Tk1fT1ZFUl9NQVhQOwo+Pj4+Pj4+ICsKPj4+Pj4+PiAgICAgICAgICAgICAgICAgIGlmICgocmRl di0+ZmFtaWx5ID09IENISVBfUlM2MDApIHx8Cj4+Pj4+Pj4gICAgICAgICAgICAgICAgICAgICAg KHJkZXYtPmZhbWlseSA9PSBDSElQX1JTNjkwKSB8fAo+Pj4+Pj4+ICAgICAgICAgICAgICAgICAg ICAgIChyZGV2LT5mYW1pbHkgPT0gQ0hJUF9SUzc0MCkpCj4+Pj4+Pj4KPj4+Pj4+IEhlbHAuLiBt YXliZS4uLiBpdCBpcyB0cmlja3kgdG8gdGVsbC4gSXQgZGVmaW5pdGVseSBkb2VzIF9ub3RfIGZp eCB0aGUKPj4+Pj4+IGlzc3VlIGNvbXBsZXRlbHkuCj4+Pj4+IFlvdSBjb3VsZCBhbHNvIHRyeSB0 aGUgb2xkIHBsbCBhbGdvcml0aG06Cj4+Pj4gSSByZXZlcnRlZCB0aGUgcGF0Y2ggYWJvdmUsIGFu ZCBzd2l0Y2hlZCB0byB0aGUgb2xkIGFsZ29yaXRobS4KPj4+Pgo+Pj4+IFRoZSBmbGlja2VyIGlz IHN0aWxsIHRoZXJlLiAoQnV0IG1heWJlIGl0cyBsZXNzIGhvcnJpYmxlLCBsaWtlIHdpdGgKPj4+ PiBSQURFT05fUExMX1BSRUZFUl9NSU5NX09WRVJfTUFYUCkuCj4+PiBUaGUgZmxpY2tlcmluZyB3 b3VsZCB2YW5pc2ggY29tcGxldGVseSBpZiB0aGF0J3MgdGhlIHJlYXNvbiBmb3IgdGhlIGlzc3Vl Cj4+PiB5b3UgYXJlIHNlZWluZy4KPj4+IFRyeSBzZXR0aW5nIHJlZl9kaXZfbWluIGFuZCByZWZf ZGl2X21heCB0byAyIGluCj4+PiAgIHJhZGVvbl9jb21wdXRlX3BsbF9hdml2bygpLgo+PiBPaywg SSBkaWQgdGhpcywgYnV0IG5vIGx1Y2ssIHN0aWxsIGZsaWNrZXJzLiBCdXQgdGhlIGZsaWNrZXIg b25seQo+PiBoYXBwZW5zIHdoZW4gc29tZXRoaW5nIGNoYW5nZXMgb24gc2NyZWVuLCBsaWtlIGRy YWdnaW5nIGEgYmlnCj4+IHdpbmRvdy4gSXMgdGhhdCBjb25zaXN0ZW50IHdpdGggd3JvbmcgUExM IHRpbWluZ3M/Cj4gRG9lcyBpdCBnbyBhd2F5IHdpdGggcmFkZW9uLmRwbT0wPyAgU291bmRzIG1v cmUgbGlrZSBlaXRoZXIgbWVtb3J5Cj4gcmVjbG9ja2luZyBoYXBwZW5pbmcgb3V0c2lkZSBvZiB2 YmxhbmssIG9yIHVuZGVyZmxvdyB0byB0aGUgZGlzcGxheQo+IGNvbnRyb2xsZXJzLgoKU291bmRz IGxpa2UgbXkgc3VzcGljaW9uIHdhcyByaWdodCwgdGhhdCBkb2Vzbid0IHNlZW0gdG8gYmUgYSBQ TEwgaXNzdWUgCmFmdGVyIGFsbC4KCkp1c3QgdG8gcnVsZSBvdXQgdGhlIG9idmlvdXMgeW91ciBz eXN0ZW0gd29ya3MgZmluZSB3aXRoIHdpbmRvd3MgYW5kIHlvdSAKZG9uJ3QgaGF2ZSBhIGV4dHJh IGxvbmcgY2FibGUgZm9yIHRoZSBtb25pdG9yIG9yIHNvbWV0aGluZyBsaWtlIHRoaXM/CgpSZWdh cmRzLApDaHJpc3RpYW4uCgo+Cj4gQWxleAo+Cj4+IGRpZmYgLS1naXQgYS9jb25maWcuMzIgYi9j b25maWcuMzIKPj4gaW5kZXggMDBlNWRkMi4uNDczNDE1OCAxMDA2NDQKPj4gLS0tIGEvY29uZmln LjMyCj4+ICsrKyBiL2NvbmZpZy4zMgo+PiBAQCAtMTA5MCw3ICsxMDkwLDcgQEAgQ09ORklHX0RF VlRNUEZTX01PVU5UPXkKPj4gICBDT05GSUdfUFJFVkVOVF9GSVJNV0FSRV9CVUlMRD15Cj4+ICAg Q09ORklHX0ZXX0xPQURFUj15Cj4+ICAgQ09ORklHX0ZJUk1XQVJFX0lOX0tFUk5FTD15Cj4+IC1D T05GSUdfRVhUUkFfRklSTVdBUkU9InJhZGVvbi9SNzAwX3JsYy5iaW4iCj4+ICtDT05GSUdfRVhU UkFfRklSTVdBUkU9InJhZGVvbi9SNzAwX3JsYy5iaW4gcmFkZW9uL1JWNzEwX3NtYy5iaW4gcmFk ZW9uL1JWNzEwX3V2ZC5iaW4iCj4+ICAgQ09ORklHX0VYVFJBX0ZJUk1XQVJFX0RJUj0iL2xpYi9m aXJtd2FyZSIKPj4gICAjIENPTkZJR19GV19MT0FERVJfVVNFUl9IRUxQRVJfRkFMTEJBQ0sgaXMg bm90IHNldAo+PiAgIENPTkZJR19BTExPV19ERVZfQ09SRURVTVA9eQo+PiBkaWZmIC0tZ2l0IGEv ZHJpdmVycy9ncHUvZHJtL3JhZGVvbi9hdG9tYmlvc19jcnRjLmMgYi9kcml2ZXJzL2dwdS9kcm0v cmFkZW9uL2F0b21iaW9zX2NydGMuYwo+PiBpbmRleCBkYWM3OGFkLi5kY2M0ZjRkIDEwMDY0NAo+ PiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcmFkZW9uL2F0b21iaW9zX2NydGMuYwo+PiArKysgYi9k cml2ZXJzL2dwdS9kcm0vcmFkZW9uL2F0b21iaW9zX2NydGMuYwo+PiBAQCAtNTY5LDYgKzU2OSw4 IEBAIHN0YXRpYyB1MzIgYXRvbWJpb3NfYWRqdXN0X3BsbChzdHJ1Y3QgZHJtX2NydGMgKmNydGMs Cj4+ICAgICAgICAgIHJhZGVvbl9jcnRjLT5wbGxfZmxhZ3MgPSAwOwo+Pgo+PiAgICAgICAgICBp ZiAoQVNJQ19JU19BVklWTyhyZGV2KSkgewo+PiArICAgICAgICAgICAgICAgLy9yYWRlb25fY3J0 Yy0+cGxsX2ZsYWdzIHw9IFJBREVPTl9QTExfUFJFRkVSX01JTk1fT1ZFUl9NQVhQOwo+PiArCj4+ ICAgICAgICAgICAgICAgICAgaWYgKChyZGV2LT5mYW1pbHkgPT0gQ0hJUF9SUzYwMCkgfHwKPj4g ICAgICAgICAgICAgICAgICAgICAgKHJkZXYtPmZhbWlseSA9PSBDSElQX1JTNjkwKSB8fAo+PiAg ICAgICAgICAgICAgICAgICAgICAocmRldi0+ZmFtaWx5ID09IENISVBfUlM3NDApKQo+PiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3JhZGVvbi9yYWRlb25fZGlzcGxheS5jIGIvZHJpdmVy cy9ncHUvZHJtL3JhZGVvbi9yYWRlb25fZGlzcGxheS5jCj4+IGluZGV4IDY3NDMxNzQuLmJlYmFm NGYgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9yYWRlb24vcmFkZW9uX2Rpc3BsYXku Ywo+PiArKysgYi9kcml2ZXJzL2dwdS9kcm0vcmFkZW9uL3JhZGVvbl9kaXNwbGF5LmMKPj4gQEAg LTk0Nyw2ICs5NDcsNyBAQCB2b2lkIHJhZGVvbl9jb21wdXRlX3BsbF9hdml2byhzdHJ1Y3QgcmFk ZW9uX3BsbCAqcGxsLAo+PiAgICAgICAgICBmYl9kaXZfbWF4ID0gcGxsLT5tYXhfZmVlZGJhY2tf ZGl2Owo+Pgo+PiAgICAgICAgICBpZiAocGxsLT5mbGFncyAmIFJBREVPTl9QTExfVVNFX0ZSQUNf RkJfRElWKSB7Cj4+ICsgICAgICAgICAgICAgICBwcmludGsoInJhZGVvbjogZnJhY3Rpb25hbCBk aXZpZGVyXG4iKTsKPj4gICAgICAgICAgICAgICAgICBmYl9kaXZfbWluICo9IDEwOwo+PiAgICAg ICAgICAgICAgICAgIGZiX2Rpdl9tYXggKj0gMTA7Cj4+ICAgICAgICAgIH0KPj4gQEAgLTk2Niw2 ICs5NjcsOSBAQCB2b2lkIHJhZGVvbl9jb21wdXRlX3BsbF9hdml2byhzdHJ1Y3QgcmFkZW9uX3Bs bCAqcGxsLAo+PiAgICAgICAgICBlbHNlCj4+ICAgICAgICAgICAgICAgICAgcmVmX2Rpdl9tYXgg PSBwbGwtPm1heF9yZWZfZGl2Owo+Pgo+PiArICAgICAgIHJlZl9kaXZfbWluID0gMjsKPj4gKyAg ICAgICByZWZfZGl2X21heCA9IDI7Cj4+ICsKPj4gICAgICAgICAgLyogZGV0ZXJtaW5lIGFsbG93 ZWQgcG9zdCBkaXZpZGVyIHJhbmdlICovCj4+ICAgICAgICAgIGlmIChwbGwtPmZsYWdzICYgUkFE RU9OX1BMTF9VU0VfUE9TVF9ESVYpIHsKPj4gICAgICAgICAgICAgICAgICBwb3N0X2Rpdl9taW4g PSBwbGwtPnBvc3RfZGl2Owo+PiBAQCAtMTAyMCw2ICsxMDI0LDggQEAgdm9pZCByYWRlb25fY29t cHV0ZV9wbGxfYXZpdm8oc3RydWN0IHJhZGVvbl9wbGwgKnBsbCwKPj4gICAgICAgICAgICAgICAg ICBkaWZmID0gYWJzKHRhcmdldF9jbG9jayAtIChwbGwtPnJlZmVyZW5jZV9mcmVxICogZmJfZGl2 KSAvCj4+ICAgICAgICAgICAgICAgICAgICAgICAgICAocmVmX2RpdiAqIHBvc3RfZGl2KSk7Cj4+ Cj4+ICsgICAgICAgICAgICAgICBwcmludGsoInBvc3RfZGl2ID0gJWQsIGRpZmYgPSAlZFxuIiwg cG9zdF9kaXYsIGRpZmYpOwo+PiArCj4+ICAgICAgICAgICAgICAgICAgaWYgKGRpZmYgPCBkaWZm X2Jlc3QgfHwgKGRpZmYgPT0gZGlmZl9iZXN0ICYmCj4+ICAgICAgICAgICAgICAgICAgICAgICEo cGxsLT5mbGFncyAmIFJBREVPTl9QTExfUFJFRkVSX01JTk1fT1ZFUl9NQVhQKSkpIHsKPj4KPj4g QEAgLTEwMjgsNiArMTAzNCw3IEBAIHZvaWQgcmFkZW9uX2NvbXB1dGVfcGxsX2F2aXZvKHN0cnVj dCByYWRlb25fcGxsICpwbGwsCj4+ICAgICAgICAgICAgICAgICAgfQo+PiAgICAgICAgICB9Cj4+ ICAgICAgICAgIHBvc3RfZGl2ID0gcG9zdF9kaXZfYmVzdDsKPj4gKyAgICAgICBwcmludGsoIlNl bGVjdGVkIHBvc3RfZGl2ID0gJWRcbiIsIHBvc3RfZGl2KTsKPj4KPj4gICAgICAgICAgLyogZ2V0 IHRoZSBmZWVkYmFjayBhbmQgcmVmZXJlbmNlIGRpdmlkZXIgZm9yIHRoZSBvcHRpbWFsIHZhbHVl ICovCj4+ICAgICAgICAgIGF2aXZvX2dldF9mYl9yZWZfZGl2KG5vbSwgZGVuLCBwb3N0X2Rpdiwg ZmJfZGl2X21heCwgcmVmX2Rpdl9tYXgsCj4+IEBAIC0xMDYyLDcgKzEwNjksNyBAQCB2b2lkIHJh ZGVvbl9jb21wdXRlX3BsbF9hdml2byhzdHJ1Y3QgcmFkZW9uX3BsbCAqcGxsLAo+PiAgICAgICAg ICAqcmVmX2Rpdl9wID0gcmVmX2RpdjsKPj4gICAgICAgICAgKnBvc3RfZGl2X3AgPSBwb3N0X2Rp djsKPj4KPj4gLSAgICAgICBEUk1fREVCVUdfS01TKCIlZCAtICVkLCBwbGwgZGl2aWRlcnMgLSBm YjogJWQuJWQgcmVmOiAlZCwgcG9zdCAlZFxuIiwKPj4gKyAgICAgICBwcmludGsoIiVkIC0gJWQs IHBsbCBkaXZpZGVycyAtIGZiOiAlZC4lZCByZWY6ICVkLCBwb3N0ICVkXG4iLAo+PiAgICAgICAg ICAgICAgICAgICAgICAgIGZyZXEsICpkb3RfY2xvY2tfcCAqIDEwLCAqZmJfZGl2X3AsICpmcmFj X2ZiX2Rpdl9wLAo+PiAgICAgICAgICAgICAgICAgICAgICAgIHJlZl9kaXYsIHBvc3RfZGl2KTsK Pj4gICB9Cj4+Cj4+Cj4+PiBCdXQgSSdtIG5vdCAxMDAlIGNvbnZpbmNlZCB0aGF0IHRoaXMgaXMg YWN0dWFsbHkgYSBQTEwgcHJvYmxlbSwgdHJ5IHRvCj4+PiBjb21waWxlIHRoZSBmaXJtd2FyZSBp dCBjb21wbGFpbnMgYWJvdXQgaW50byB0aGUga2VybmVsIGFzIHdlbGwuCj4+IERpZCB0aGF0LCB0 b28uCj4+Cj4+IEJlc3QgcmVnYXJkcywKPj4gICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFBhdmVsCj4+IC0tCj4+ IChlbmdsaXNoKSBodHRwOi8vd3d3LmxpdmVqb3VybmFsLmNvbS9+cGF2ZWxtYWNoZWsKPj4gKGNl c2t5LCBwaWN0dXJlcykgaHR0cDovL2F0cmV5Lmthcmxpbi5tZmYuY3VuaS5jei9+cGF2ZWwvcGlj dHVyZS9ob3JzZXMvYmxvZy5odG1sCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVl ZGVza3RvcC5vcmcKaHR0cDovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZv L2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032217AbbKEKoK (ORCPT ); Thu, 5 Nov 2015 05:44:10 -0500 Received: from pegasos-out.vodafone.de ([80.84.1.38]:45347 "EHLO pegasos-out.vodafone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1031985AbbKEKnl (ORCPT ); Thu, 5 Nov 2015 05:43:41 -0500 X-Spam-Flag: NO X-Spam-Score: 0.201 Authentication-Results: rohrpostix2.prod.vfnet.de (amavisd-new); dkim=pass header.i=@vodafone.de X-DKIM: OpenDKIM Filter v2.6.8 pegasos-out.vodafone.de 3B8664C3347 Subject: Re: Mobility Radeon HD 4530/4570/545v: flicker in 1920x1080 To: Alex Deucher , Pavel Machek References: <20151031201344.GA30459@amd> <563522C5.1000206@amd.com> <20151031212259.GA6253@amd> <20151103220919.GA4824@amd> <20151103230329.GA4167@amd> <5639B580.1050409@vodafone.de> <20151104221000.GA3608@amd> Cc: "Deucher, Alexander" , "linux-fbdev@vger.kernel.org" , =?UTF-8?Q?Christian_K=c3=b6nig?= , Maling list - DRI developers , kernel list From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: <563B32C7.3080202@vodafone.de> Date: Thu, 5 Nov 2015 11:43:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04.11.2015 23:13, Alex Deucher wrote: > On Wed, Nov 4, 2015 at 5:10 PM, Pavel Machek wrote: >> Hi! >> >>>>>>> index dac78ad..b86f06a 100644 >>>>>>> --- a/drivers/gpu/drm/radeon/atombios_crtc.c >>>>>>> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c >>>>>>> @@ -569,6 +569,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, >>>>>>> radeon_crtc->pll_flags = 0; >>>>>>> >>>>>>> if (ASIC_IS_AVIVO(rdev)) { >>>>>>> + radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; >>>>>>> + >>>>>>> if ((rdev->family == CHIP_RS600) || >>>>>>> (rdev->family == CHIP_RS690) || >>>>>>> (rdev->family == CHIP_RS740)) >>>>>>> >>>>>> Help.. maybe... it is tricky to tell. It definitely does _not_ fix the >>>>>> issue completely. >>>>> You could also try the old pll algorithm: >>>> I reverted the patch above, and switched to the old algorithm. >>>> >>>> The flicker is still there. (But maybe its less horrible, like with >>>> RADEON_PLL_PREFER_MINM_OVER_MAXP). >>> The flickering would vanish completely if that's the reason for the issue >>> you are seeing. >>> Try setting ref_div_min and ref_div_max to 2 in >>> radeon_compute_pll_avivo(). >> Ok, I did this, but no luck, still flickers. But the flicker only >> happens when something changes on screen, like dragging a big >> window. Is that consistent with wrong PLL timings? > Does it go away with radeon.dpm=0? Sounds more like either memory > reclocking happening outside of vblank, or underflow to the display > controllers. Sounds like my suspicion was right, that doesn't seem to be a PLL issue after all. Just to rule out the obvious your system works fine with windows and you don't have a extra long cable for the monitor or something like this? Regards, Christian. > > Alex > >> diff --git a/config.32 b/config.32 >> index 00e5dd2..4734158 100644 >> --- a/config.32 >> +++ b/config.32 >> @@ -1090,7 +1090,7 @@ CONFIG_DEVTMPFS_MOUNT=y >> CONFIG_PREVENT_FIRMWARE_BUILD=y >> CONFIG_FW_LOADER=y >> CONFIG_FIRMWARE_IN_KERNEL=y >> -CONFIG_EXTRA_FIRMWARE="radeon/R700_rlc.bin" >> +CONFIG_EXTRA_FIRMWARE="radeon/R700_rlc.bin radeon/RV710_smc.bin radeon/RV710_uvd.bin" >> CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware" >> # CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set >> CONFIG_ALLOW_DEV_COREDUMP=y >> diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c >> index dac78ad..dcc4f4d 100644 >> --- a/drivers/gpu/drm/radeon/atombios_crtc.c >> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c >> @@ -569,6 +569,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, >> radeon_crtc->pll_flags = 0; >> >> if (ASIC_IS_AVIVO(rdev)) { >> + //radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; >> + >> if ((rdev->family == CHIP_RS600) || >> (rdev->family == CHIP_RS690) || >> (rdev->family == CHIP_RS740)) >> diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c >> index 6743174..bebaf4f 100644 >> --- a/drivers/gpu/drm/radeon/radeon_display.c >> +++ b/drivers/gpu/drm/radeon/radeon_display.c >> @@ -947,6 +947,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, >> fb_div_max = pll->max_feedback_div; >> >> if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { >> + printk("radeon: fractional divider\n"); >> fb_div_min *= 10; >> fb_div_max *= 10; >> } >> @@ -966,6 +967,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, >> else >> ref_div_max = pll->max_ref_div; >> >> + ref_div_min = 2; >> + ref_div_max = 2; >> + >> /* determine allowed post divider range */ >> if (pll->flags & RADEON_PLL_USE_POST_DIV) { >> post_div_min = pll->post_div; >> @@ -1020,6 +1024,8 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, >> diff = abs(target_clock - (pll->reference_freq * fb_div) / >> (ref_div * post_div)); >> >> + printk("post_div = %d, diff = %d\n", post_div, diff); >> + >> if (diff < diff_best || (diff == diff_best && >> !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { >> >> @@ -1028,6 +1034,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, >> } >> } >> post_div = post_div_best; >> + printk("Selected post_div = %d\n", post_div); >> >> /* get the feedback and reference divider for the optimal value */ >> avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max, >> @@ -1062,7 +1069,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, >> *ref_div_p = ref_div; >> *post_div_p = post_div; >> >> - DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", >> + printk("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", >> freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, >> ref_div, post_div); >> } >> >> >>> But I'm not 100% convinced that this is actually a PLL problem, try to >>> compile the firmware it complains about into the kernel as well. >> Did that, too. >> >> Best regards, >> Pavel >> -- >> (english) http://www.livejournal.com/~pavelmachek >> (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html