From mboxrd@z Thu Jan  1 00:00:00 1970
From: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Subject: Re: [PATCH v6 1/4] Documentation: dt-bindings: Describe SROMc
 configuration
Date: Fri, 06 Nov 2015 17:18:12 +0900
Message-ID: <563C6244.6060806@samsung.com>
References: <cover.1446724046.git.p.fedin@samsung.com>
 <26ce9f26ee8537b2f81ad0bf470d1c6b1c8a1a31.1446724046.git.p.fedin@samsung.com>
 <563BEE44.4040207@samsung.com> <001001d1186b$358b6470$a0a22d50$@samsung.com>
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To: Pavel Fedin <p.fedin@samsung.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: 'Rob Herring' <robh+dt@kernel.org>, 'Pawel Moll' <pawel.moll@arm.com>, 'Mark Rutland' <mark.rutland@arm.com>, 'Ian Campbell' <ijc+devicetree@hellion.org.uk>, 'Kumar Gala' <galak@codeaurora.org>, 'Kukjin Kim' <kgene@kernel.org>
List-Id: linux-samsung-soc@vger.kernel.org

On 06.11.2015 17:14, Pavel Fedin wrote:
>  Hello!
> 
>>> +- samsung,srom-timing : array of 6 integers, specifying bank timings in the
>>> +                        following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
>>> +                        Each value is specified in cycles and has the following
>>> +                        meaning and valid range:
>>> +                        Tacp : Page mode access cycle at Page mode (0 - 15)
>>> +                        Tcah : Address holding time after CSn (0 - 15)
>>> +                        Tcoh : Chip selection hold on OEn (0 - 15)
>>> +                        Tacc : Access cycle (0 - 32)
>>
>> All of the manuals have error here. Probably it can be either: 1-32 or
>> 0-31. I would bet on 0-31, what do you think?
> 
>  Damn, everything starts from 0, so i automatically put '0 - 32'. The actual time, however, varies from 1 to 32, but the value is
> from 0 to 31, i. e. <time> - 1
>  What shall we do? Just document this, or adjust the code to take number of cycles and subtract 1? To tell the truth, i'm already
> sick of these small fixups, and i would prefer just to fix documentation.

Whatever you choose. Just make it correct. :) The problem is that
Datasheet has errors for these values...

Best regards,
Krzysztof

From mboxrd@z Thu Jan  1 00:00:00 1970
From: k.kozlowski@samsung.com (Krzysztof Kozlowski)
Date: Fri, 06 Nov 2015 17:18:12 +0900
Subject: [PATCH v6 1/4] Documentation: dt-bindings: Describe SROMc
 configuration
In-Reply-To: <001001d1186b$358b6470$a0a22d50$@samsung.com>
References: <cover.1446724046.git.p.fedin@samsung.com>
 <26ce9f26ee8537b2f81ad0bf470d1c6b1c8a1a31.1446724046.git.p.fedin@samsung.com>
 <563BEE44.4040207@samsung.com> <001001d1186b$358b6470$a0a22d50$@samsung.com>
Message-ID: <563C6244.6060806@samsung.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

On 06.11.2015 17:14, Pavel Fedin wrote:
>  Hello!
> 
>>> +- samsung,srom-timing : array of 6 integers, specifying bank timings in the
>>> +                        following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
>>> +                        Each value is specified in cycles and has the following
>>> +                        meaning and valid range:
>>> +                        Tacp : Page mode access cycle at Page mode (0 - 15)
>>> +                        Tcah : Address holding time after CSn (0 - 15)
>>> +                        Tcoh : Chip selection hold on OEn (0 - 15)
>>> +                        Tacc : Access cycle (0 - 32)
>>
>> All of the manuals have error here. Probably it can be either: 1-32 or
>> 0-31. I would bet on 0-31, what do you think?
> 
>  Damn, everything starts from 0, so i automatically put '0 - 32'. The actual time, however, varies from 1 to 32, but the value is
> from 0 to 31, i. e. <time> - 1
>  What shall we do? Just document this, or adjust the code to take number of cycles and subtract 1? To tell the truth, i'm already
> sick of these small fixups, and i would prefer just to fix documentation.

Whatever you choose. Just make it correct. :) The problem is that
Datasheet has errors for these values...

Best regards,
Krzysztof