From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Christian_K=c3=b6nig?= Subject: Re: [PATCH] drm/amdgpu: Fix default page access routing Date: Fri, 6 Nov 2015 09:28:28 +0100 Message-ID: <563C64AC.7080307@vodafone.de> References: <1446750375-9967-1-git-send-email-jay@jcornwall.me> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: Received: from pegasos-out.vodafone.de (pegasos-out.vodafone.de [80.84.1.38]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EB696E463 for ; Fri, 6 Nov 2015 00:28:40 -0800 (PST) In-Reply-To: <1446750375-9967-1-git-send-email-jay@jcornwall.me> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Jay Cornwall , dri-devel@lists.freedesktop.org Cc: stable@vger.kernel.org List-Id: dri-devel@lists.freedesktop.org T24gMDUuMTEuMjAxNSAyMDowNiwgSmF5IENvcm53YWxsIHdyb3RlOgo+IFRoZSBWTSBkZWZhdWx0 IHBhZ2UgKHVzZWQgd2hlbiBhIFZNIHRyYW5zbGF0aW9uIGZhaWxzKSBpcyBhbGxvY2F0ZWQgaW4K PiBzeXN0ZW0gbWVtb3J5LiBUaGUgVk0gaXMgbWlzY29uZmlndXJlZCB0byBpbnRlcnByZXQgdGhl IHBoeXNpY2FsIGFkZHJlc3MKPiBhcyByZWZlcmVuY2luZyBhIFZSQU0gcGh5c2ljYWwgcGFnZS4K Pgo+IFJvdXRlIGRlZmF1bHQgcGFnZSBhY2Nlc3NlcyB0byBzeXN0ZW0gbWVtb3J5Lgo+Cj4gU2ln bmVkLW9mZi1ieTogSmF5IENvcm53YWxsIDxqYXlAamNvcm53YWxsLm1lPgo+IENjOiA8c3RhYmxl QHZnZXIua2VybmVsLm9yZz4gIyB2NC4yKwoKTmljZSBjYXRjaCwgcGF0Y2ggaXMgUmV2aWV3ZWQt Ynk6IENocmlzdGlhbiBLw7ZuaWcgPGNocmlzdGlhbi5rb2VuaWdAYW1kLmNvbT4KCkRvIHdlIGFs c28gbmVlZCB0aGlzIGZvciBSYWRlb24/CgpSZWdhcmRzLApDaHJpc3RpYW4uCgo+IC0tLQo+ICAg ZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvZ21jX3Y3XzAuYyB8IDEgKwo+ICAgZHJpdmVycy9n cHUvZHJtL2FtZC9hbWRncHUvZ21jX3Y4XzAuYyB8IDEgKwo+ICAgMiBmaWxlcyBjaGFuZ2VkLCAy IGluc2VydGlvbnMoKykKPgo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vYW1kL2FtZGdw dS9nbWNfdjdfMC5jIGIvZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvZ21jX3Y3XzAuYwo+IGlu ZGV4IGZhYjU0NzEuLmI5ODM2ZjYgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2FtZC9h bWRncHUvZ21jX3Y3XzAuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9hbWQvYW1kZ3B1L2dtY192 N18wLmMKPiBAQCAtNDc0LDYgKzQ3NCw3IEBAIHN0YXRpYyBpbnQgZ21jX3Y3XzBfZ2FydF9lbmFi bGUoc3RydWN0IGFtZGdwdV9kZXZpY2UgKmFkZXYpCj4gICAJdG1wID0gUkVHX1NFVF9GSUVMRCh0 bXAsIFZNX0wyX0NOVEwsIEVOQUJMRV9MMl9QREUwX0NBQ0hFX0xSVV9VUERBVEVfQllfV1JJVEUs IDEpOwo+ICAgCXRtcCA9IFJFR19TRVRfRklFTEQodG1wLCBWTV9MMl9DTlRMLCBFRkZFQ1RJVkVf TDJfUVVFVUVfU0laRSwgNyk7Cj4gICAJdG1wID0gUkVHX1NFVF9GSUVMRCh0bXAsIFZNX0wyX0NO VEwsIENPTlRFWFQxX0lERU5USVRZX0FDQ0VTU19NT0RFLCAxKTsKPiArCXRtcCA9IFJFR19TRVRf RklFTEQodG1wLCBWTV9MMl9DTlRMLCBFTkFCTEVfREVGQVVMVF9QQUdFX09VVF9UT19TWVNURU1f TUVNT1JZLCAxKTsKPiAgIAlXUkVHMzIobW1WTV9MMl9DTlRMLCB0bXApOwo+ICAgCXRtcCA9IFJF R19TRVRfRklFTEQoMCwgVk1fTDJfQ05UTDIsIElOVkFMSURBVEVfQUxMX0wxX1RMQlMsIDEpOwo+ ICAgCXRtcCA9IFJFR19TRVRfRklFTEQodG1wLCBWTV9MMl9DTlRMMiwgSU5WQUxJREFURV9MMl9D QUNIRSwgMSk7Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9hbWQvYW1kZ3B1L2dtY192 OF8wLmMgYi9kcml2ZXJzL2dwdS9kcm0vYW1kL2FtZGdwdS9nbWNfdjhfMC5jCj4gaW5kZXggN2Jj OWU5Zi4uY2I0ZTJiYiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vYW1kL2FtZGdwdS9n bWNfdjhfMC5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2FtZC9hbWRncHUvZ21jX3Y4XzAuYwo+ IEBAIC01ODgsNiArNTg4LDcgQEAgc3RhdGljIGludCBnbWNfdjhfMF9nYXJ0X2VuYWJsZShzdHJ1 Y3QgYW1kZ3B1X2RldmljZSAqYWRldikKPiAgIAl0bXAgPSBSRUdfU0VUX0ZJRUxEKHRtcCwgVk1f TDJfQ05UTCwgRU5BQkxFX0wyX1BERTBfQ0FDSEVfTFJVX1VQREFURV9CWV9XUklURSwgMSk7Cj4g ICAJdG1wID0gUkVHX1NFVF9GSUVMRCh0bXAsIFZNX0wyX0NOVEwsIEVGRkVDVElWRV9MMl9RVUVV RV9TSVpFLCA3KTsKPiAgIAl0bXAgPSBSRUdfU0VUX0ZJRUxEKHRtcCwgVk1fTDJfQ05UTCwgQ09O VEVYVDFfSURFTlRJVFlfQUNDRVNTX01PREUsIDEpOwo+ICsJdG1wID0gUkVHX1NFVF9GSUVMRCh0 bXAsIFZNX0wyX0NOVEwsIEVOQUJMRV9ERUZBVUxUX1BBR0VfT1VUX1RPX1NZU1RFTV9NRU1PUlks IDEpOwo+ICAgCVdSRUczMihtbVZNX0wyX0NOVEwsIHRtcCk7Cj4gICAJdG1wID0gUlJFRzMyKG1t Vk1fTDJfQ05UTDIpOwo+ICAgCXRtcCA9IFJFR19TRVRfRklFTEQodG1wLCBWTV9MMl9DTlRMMiwg SU5WQUxJREFURV9BTExfTDFfVExCUywgMSk7CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0 cy5mcmVlZGVza3RvcC5vcmcKaHR0cDovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xp c3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from pegasos-out.vodafone.de ([80.84.1.38]:35958 "EHLO pegasos-out.vodafone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1032257AbbKFIg1 (ORCPT ); Fri, 6 Nov 2015 03:36:27 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by pegasos-out.vodafone.de (Rohrpostix2 Daemon) with ESMTP id 426674C3CF1 for ; Fri, 6 Nov 2015 09:28:38 +0100 (CET) Received: from pegasos-out.vodafone.de ([127.0.0.1]) by localhost (rohrpostix2.prod.vfnet.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cgJrNrC8FCaA for ; Fri, 6 Nov 2015 09:28:36 +0100 (CET) Subject: Re: [PATCH] drm/amdgpu: Fix default page access routing To: Jay Cornwall , dri-devel@lists.freedesktop.org References: <1446750375-9967-1-git-send-email-jay@jcornwall.me> Cc: stable@vger.kernel.org From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: <563C64AC.7080307@vodafone.de> Date: Fri, 6 Nov 2015 09:28:28 +0100 MIME-Version: 1.0 In-Reply-To: <1446750375-9967-1-git-send-email-jay@jcornwall.me> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: On 05.11.2015 20:06, Jay Cornwall wrote: > The VM default page (used when a VM translation fails) is allocated in > system memory. The VM is misconfigured to interpret the physical address > as referencing a VRAM physical page. > > Route default page accesses to system memory. > > Signed-off-by: Jay Cornwall > Cc: # v4.2+ Nice catch, patch is Reviewed-by: Christian König Do we also need this for Radeon? Regards, Christian. > --- > drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 + > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > index fab5471..b9836f6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > @@ -474,6 +474,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); > WREG32(mmVM_L2_CNTL, tmp); > tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > index 7bc9e9f..cb4e2bb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > @@ -588,6 +588,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); > + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); > WREG32(mmVM_L2_CNTL, tmp); > tmp = RREG32(mmVM_L2_CNTL2); > tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);