From: Julien Grall <julien.grall@citrix.com>
To: xen-devel@lists.xenproject.org
Cc: ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com
Subject: Re: [PATCH v5 5/6] xen/arm: vgic: Introduce helpers to extract/update/clear/set vGIC register ...
Date: Wed, 11 Nov 2015 16:09:22 +0000 [thread overview]
Message-ID: <56436832.9050705@citrix.com> (raw)
In-Reply-To: <1447084181-13677-6-git-send-email-julien.grall@citrix.com>
Hi,
I've just noticed one error in this patch :/
On 09/11/15 15:49, Julien Grall wrote:
> @@ -482,16 +500,16 @@ static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v,
> return 0;
>
> case GICD_IPRIORITYR ... GICD_IPRIORITYRN:
> + {
> + uint32_t *ipriorityr;
> +
> if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
> rank = vgic_rank_offset(v, 8, reg - GICD_IPRIORITYR, DABT_WORD);
> if ( rank == NULL ) goto write_ignore;
> vgic_lock_rank(v, rank, flags);
> - if ( dabt.size == DABT_WORD )
> - rank->ipriorityr[REG_RANK_INDEX(8, reg - GICD_IPRIORITYR,
> - DABT_WORD)] = r;
> - else
> - vgic_byte_write(&rank->ipriorityr[REG_RANK_INDEX(8,
> - reg - GICD_IPRIORITYR, DABT_WORD)], r, reg);
> + ipriorityr = &rank->ipriorityr[REG_RANK_INDEX(8, reg - GICD_IPRIORITYR,
> + DABT_WORD)];
> + vgic_reg32_update(ipriorityr, r, info);
> vgic_unlock_rank(v, rank, flags);
> return 1;
There is a missing } here. Somehow gcc didn't complain but there is a
spurious closed brace in the next case.
> case GICD_ICFGR: /* Restricted to configure SGIs */
> @@ -503,9 +521,13 @@ static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v,
> rank = vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD);
> if ( rank == NULL ) goto write_ignore;
> vgic_lock_rank(v, rank, flags);
> - rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, DABT_WORD)] = r;
> + vgic_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR,
> + DABT_WORD)],
> + r, info);
> vgic_unlock_rank(v, rank, flags);
> return 1;
> + }
> +
Here is the spurious one.
I will either resend this whole series or only this patch depending on
the reviews.
Regards,
--
Julien Grall
next prev parent reply other threads:[~2015-11-11 16:10 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-09 15:49 [PATCH v5 0/6] xen/arm: vgic: Support 32-bit access for 64-bit register Julien Grall
2015-11-09 15:49 ` [PATCH v5 1/6] xen/arm: vgic-v2: Implement correctly ITARGETSR0 - ITARGETSR7 read-only Julien Grall
2015-11-13 11:18 ` Stefano Stabellini
2015-11-16 13:23 ` Ian Campbell
2015-11-18 16:20 ` Julien Grall
2015-11-09 15:49 ` [PATCH v5 2/6] xen/arm: vgic-v2: Handle correctly byte write in ITARGETSR Julien Grall
2015-11-13 12:08 ` Stefano Stabellini
2015-11-09 15:49 ` [PATCH v5 3/6] xen/arm: vgic-v2: Don't ignore a write in ITARGETSR if one field is 0 Julien Grall
2015-11-13 14:37 ` Stefano Stabellini
2015-11-13 14:52 ` Julien Grall
2015-11-13 15:05 ` Stefano Stabellini
2015-11-13 15:39 ` Julien Grall
2015-11-09 15:49 ` [PATCH v5 4/6] xen/arm: vgic: Optimize the way to store the target vCPU in the rank Julien Grall
2015-11-13 15:44 ` Stefano Stabellini
2015-11-13 15:49 ` Julien Grall
2015-11-09 15:49 ` [PATCH v5 5/6] xen/arm: vgic: Introduce helpers to extract/update/clear/set vGIC register Julien Grall
2015-11-11 16:09 ` Julien Grall [this message]
2015-11-16 13:14 ` Ian Campbell
2015-11-09 15:49 ` [PATCH v5 6/6] xen/arm: vgic-v3: Support 32-bit access for 64-bit registers Julien Grall
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