diff for duplicates of <5645A6F6.6020202@nvidia.com> diff --git a/a/1.txt b/N1/1.txt index db4d690..49b5d79 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ On 12/11/15 23:20, Kevin Hilman wrote: -> Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> writes: +> Jon Hunter <jonathanh@nvidia.com> writes: > >> Some IRQ chips may be located in a power domain outside of the CPU subsystem >> and hence will require device specific runtime power management. Ideally, diff --git a/a/content_digest b/N1/content_digest index 971cce9..99a429a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,24 +1,23 @@ "ref\01447166377-19707-1-git-send-email-jonathanh@nvidia.com\0" "ref\01447166377-19707-2-git-send-email-jonathanh@nvidia.com\0" "ref\07hio56dctz.fsf@deeprootsystems.com\0" - "ref\07hio56dctz.fsf-1D3HCaltpLuhEniVeURVKkEOCMrvLtNR@public.gmane.org\0" - "From\0Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "From\0Jon Hunter <jonathanh@nvidia.com>\0" "Subject\0Re: [RFC PATCH 1/2] genirq: Add runtime resume/suspend support for IRQ chips\0" "Date\0Fri, 13 Nov 2015 09:01:42 +0000\0" - "To\0Kevin Hilman <khilman-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\0" - "Cc\0Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>" - Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org> - Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> - Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> - Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - Geert Uytterhoeven <geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org> - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - " linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0Kevin Hilman <khilman@kernel.org>\0" + "Cc\0Thomas Gleixner <tglx@linutronix.de>" + Jason Cooper <jason@lakedaemon.net> + Marc Zyngier <marc.zyngier@arm.com> + Stephen Warren <swarren@wwwdotorg.org> + Thierry Reding <thierry.reding@gmail.com> + Geert Uytterhoeven <geert@linux-m68k.org> + <linux-kernel@vger.kernel.org> + " <linux-tegra@vger.kernel.org>\0" "\00:1\0" "b\0" "\n" "On 12/11/15 23:20, Kevin Hilman wrote:\n" - "> Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> writes:\n" + "> Jon Hunter <jonathanh@nvidia.com> writes:\n" "> \n" ">> Some IRQ chips may be located in a power domain outside of the CPU subsystem\n" ">> and hence will require device specific runtime power management. Ideally,\n" @@ -68,4 +67,4 @@ "Cheers\n" Jon -fc2b4d126299e64bd13666fe19a1f2fed33e1d8936b24c8b0e6cd926b9d53aeb +f3df8af7a95a5d3013c63d3c1a5b5e61869e439cc04da3221dbd5b4f0cfc1c0c
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