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X-Received-From: 2a00:1450:4010:c07::22d Cc: qemu-arm@nongnu.org, QEMU Developers Subject: Re: [Qemu-arm] [PATCH 1/2] target-arm: Update condexec before CP access check in AA32 translation X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: i4CIhiVMVWHM On 17.11.2015 16:31, Peter Maydell wrote: > On 17 November 2015 at 10:59, Sergey Fedorov wrote: >> On 16.11.2015 22:34, Sergey Fedorov wrote: >>> Coprocessor access instructions are allowed inside IT block. >>> gen_helper_access_check_cp_reg() can raise an exceptions thus condexec >>> bits should be updated before. >>> >>> Signed-off-by: Sergey Fedorov >>> --- >>> target-arm/translate.c | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/target-arm/translate.c b/target-arm/translate.c >>> index 4351854..f1f8129 100644 >>> --- a/target-arm/translate.c >>> +++ b/target-arm/translate.c >>> @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) >>> break; >>> } >>> >>> + gen_set_condexec(dc); >> Ah, there must be gen_set_condexec(s). > Yep. Are you going to resend? I got sort of ahead of myself with the patch. Yes, I will resend it now. Best, Sergey From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55993) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZygSb-0007eY-1N for qemu-devel@nongnu.org; Tue, 17 Nov 2015 08:38:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZygSZ-0002nF-As for qemu-devel@nongnu.org; Tue, 17 Nov 2015 08:38:12 -0500 References: <1447702479-6997-1-git-send-email-serge.fdrv@gmail.com> <1447702479-6997-2-git-send-email-serge.fdrv@gmail.com> <564B0874.3050902@gmail.com> From: Sergey Fedorov Message-ID: <564B2DBA.1030003@gmail.com> Date: Tue, 17 Nov 2015 16:38:02 +0300 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/2] target-arm: Update condexec before CP access check in AA32 translation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, QEMU Developers On 17.11.2015 16:31, Peter Maydell wrote: > On 17 November 2015 at 10:59, Sergey Fedorov wrote: >> On 16.11.2015 22:34, Sergey Fedorov wrote: >>> Coprocessor access instructions are allowed inside IT block. >>> gen_helper_access_check_cp_reg() can raise an exceptions thus condexec >>> bits should be updated before. >>> >>> Signed-off-by: Sergey Fedorov >>> --- >>> target-arm/translate.c | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/target-arm/translate.c b/target-arm/translate.c >>> index 4351854..f1f8129 100644 >>> --- a/target-arm/translate.c >>> +++ b/target-arm/translate.c >>> @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) >>> break; >>> } >>> >>> + gen_set_condexec(dc); >> Ah, there must be gen_set_condexec(s). > Yep. Are you going to resend? I got sort of ahead of myself with the patch. Yes, I will resend it now. Best, Sergey