From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35883) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZyzGr-0002Lh-Mv for qemu-devel@nongnu.org; Wed, 18 Nov 2015 04:43:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZyzGo-0007ei-B1 for qemu-devel@nongnu.org; Wed, 18 Nov 2015 04:43:21 -0500 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]:34304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZyzGo-0007do-3O for qemu-devel@nongnu.org; Wed, 18 Nov 2015 04:43:18 -0500 Received: by wmvv187 with SMTP id v187so268784443wmv.1 for ; Wed, 18 Nov 2015 01:43:17 -0800 (PST) Sender: Richard Henderson References: <1436429849-18052-1-git-send-email-rth@twiddle.net> <564B675B.30207@redhat.com> From: Richard Henderson Message-ID: <564C482A.9040504@twiddle.net> Date: Wed, 18 Nov 2015 10:43:06 +0100 MIME-Version: 1.0 In-Reply-To: <564B675B.30207@redhat.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 00/14] target-i386: Implement MPX extension List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: ehabkost@redhat.com On 11/17/2015 06:43 PM, Paolo Bonzini wrote: > Hi Richard, it would be nice to have these patches---or at least the > XSAVE support---in 2.6. I also have a PKRU implementation for TCG, but > currently I'm only implementing RDPKRU/WRPKRU because I would like to > build the XSAVE support on top of your patches. Sure. I'll see about updating that branch this weekend. > Regarding SMM support, there are three ways to go: > > 1) pester Intel some more so that they disclose the format of the SMM > state save area; They have done so, and relatively well. Section 34.4.1.1 of the software developer's manual (I'm looking at 325462-055, June 2015). The issue, perhaps, is that the Intel and AMD layouts are totally different. Now, given that we've been using the AMD layout with Intel emulations maybe that means that it really doesn't matter what layout we use, so long as we're self-consistent. Is there anything besides BIOS code that runs in SMM anyway? Do we have to be compatible with anything besides SeaBIOS in this area? > 2) just place BNDCFGS at a random offset that is left as reserved in > AMD's manual; > > 3) do not save BNDCFGS at all since no one uses it anyway. *shrug* I'm not a fan of 3 simply because it means that one can't experiment with it, since turning it on means either that SMM produces weird results or kernel state gets corrupted. > The holes in the computation of KVM's hflags are probably harmless, but > nice to have anyway. Thanks for fixing them. Are there others that I > missed? Not that I saw. r~