From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH v3 0/7] KVM, pkeys: add memory protection-key support Date: Wed, 18 Nov 2015 12:01:47 +0100 Message-ID: <564C5A9B.9000407@redhat.com> References: <1447825444-13550-1-git-send-email-huaitong.han@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: kvm@vger.kernel.org To: Huaitong Han , gleb@kernel.org Return-path: Received: from mx1.redhat.com ([209.132.183.28]:37608 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752420AbbKRLCC (ORCPT ); Wed, 18 Nov 2015 06:02:02 -0500 In-Reply-To: <1447825444-13550-1-git-send-email-huaitong.han@intel.com> Sender: kvm-owner@vger.kernel.org List-ID: On 18/11/2015 06:43, Huaitong Han wrote: > Changes in v3: > *Add comments for patch that disable PKU feature without ept. >=20 > Changes in v2: > *Add pku.c for kvm-unit-tests. > *Optimize permission_fault codes for patch4. > *Delete is_long_mode and PK for patch5. > *Squash cpuid and cr4 patches. >=20 > The protection-key feature provides an additional mechanism by which = IA-32e > paging controls access to usermode addresses. >=20 > Hardware support for protection keys for user pages is enumerated wit= h CPUID > feature flag CPUID.7.0.ECX[3]:PKU. Software support is CPUID.7.0.ECX[= 4]:OSPKE > with the setting of CR4.PKE(bit 22). >=20 > When CR4.PKE =3D 1, every linear address is associated with the 4-bit= protection > key located in bits 62:59 of the paging-structure entry that mapped t= he page > containing the linear address. The PKRU register determines, for each > protection key, whether user-mode addresses with that protection key = may be > read or written. >=20 > The PKRU register (protection key rights for user pages) is a 32-bit = register > with the following format: for each i (0 =E2=89=A4 i =E2=89=A4 15), P= KRU[2i] is the > access-disable bit for protection key i (ADi); PKRU[2i+1] is the writ= e-disable > bit for protection key i (WDi). >=20 > Software can use the RDPKRU and WRPKRU instructions with ECX =3D 0 to= read and > write PKRU. In addition, the PKRU register is XSAVE-managed state and= can thus > be read and written by instructions in the XSAVE feature set. >=20 > PFEC.PK (bit 5) is defined as protection key violations. >=20 > The specification of Protection Keys can be found at SDM (4.6.2, volu= me 3) > http://www.intel.com/content/dam/www/public/us/en/documents/manuals/6= 4-ia-32-architectures-software-developer-manual-325462.pdf. >=20 > The kernel native patchset have not yet been merged to upstream, you = can found > at git://git.kernel.org/pub/scm/linux/kernel/git/daveh/x86-pkeys.git = pkeys-v007. >=20 > Huaitong Han (7): > KVM, pkeys: expose CPUID/CR4 to guest > KVM, pkeys: disable pkeys for guests in non-paging mode > KVM, pkeys: update memeory permission bitmask for pkeys > KVM, pkeys: add pkeys support for permission_fault logic > KVM, pkeys: Add pkeys support for gva_to_gpa funcions > KVM, pkeys: add pkeys support for xsave state > KVM, pkeys: disable PKU feature without ept >=20 > arch/x86/include/asm/kvm_host.h | 11 +++++--- > arch/x86/kvm/cpuid.c | 24 ++++++++++++++++-- > arch/x86/kvm/cpuid.h | 8 ++++++ > arch/x86/kvm/mmu.c | 32 +++++++++++++++++++++-- > arch/x86/kvm/mmu.h | 56 +++++++++++++++++++++++++++++++= ++++++---- > arch/x86/kvm/paging_tmpl.h | 18 ++++++++++--- > arch/x86/kvm/vmx.c | 10 ++++---- > arch/x86/kvm/x86.c | 27 ++++++++++++++------ > arch/x86/kvm/x86.h | 3 ++- > 9 files changed, 161 insertions(+), 28 deletions(-) >=20 Looks good, but it will have to wait for kernel PKU support. Thanks, Paolo