From: hl <hl@rock-chips.com>
To: myungjoo.ham@samsung.com, "heiko@sntech.de" <heiko@sntech.de>,
"dianders@chromium.org" <dianders@chromium.org>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
박경민 <kyungmin.park@samsung.com>
Cc: "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"sboyd@codeaurora.org" <sboyd@codeaurora.org>,
"dbasehore@chromium.org" <dbasehore@chromium.org>,
"linux-rockchip@lists.infradead.org"
<linux-rockchip@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] clk: rockchip: dmc: support rk3399 dmc clock driver
Date: Mon, 23 Nov 2015 17:26:53 +0800 [thread overview]
Message-ID: <5652DBDD.3070603@rock-chips.com> (raw)
In-Reply-To: <68719599.130141448266183403.JavaMail.weblogic@epmlwas06a>
Hi MyungJoo,
On 23/11/15 16:09, MyungJoo Ham wrote:
>> +static unsigned long rk3399_dmcclk_recalc_rate(struct clk_hw *hw,
>> + unsigned long parent_rate)
>> +{
>> + struct rk3399_dmcclk *dmc = to_rk3399_dmcclk(&hw);
>> + u32 val;
>> +
>> + /*
>> + * Get parent rate since it changed in this clks set_rate op. The parent
>> + * rate passed into this function is cached before set_rate is called in
>> + * the common clk code, so we have to get it here.
>> + */
>> + parent_rate = clk_get_rate(clk_get_parent(hw->clk));
>> +
>> + val = readl(dmc->cru + CRU_CLKSEL6_CON);
>> + val = (val >> CLK_DDRC_DIV_CON_SHIFT) & CLK_DDRC_DIV_CON_MASK;
>> +
>> + return parent_rate / (val + 1);
>> +}
>> +
>> +/*
>> + * TODO: set ddr frequcney in dcf which run in ATF
>> + */
>> +static int rk3399_dmcclk_set_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> + return 0;
>> +}
> Is it correct that you didn't fill this up because your
> Trustzone driver (SMC) is not ready yet?
Yep, the SMC is not ready yet.
>
> Then, why don't you fill that function assuming that TrustZone is not activated
> and add SMC call functions with if or #if after its TrustZone driver is ready?
>
> Or does your SoC mandate the usage ot TrustZone, restricting the usage
> of CRU_CLKSEL6_CON write? (I don't see why SoC vendors will do this..)
>
>
> I'll be ready to merge the RK3399 devfreq driver if you
> fill this up (assuming that TZ is not enabled) or
> add TZ driver and SMC calls.
Thank you for your reply, it is good idea use if or #if to
distinguish the TrustZone whether ready,
i will handle it in next version. I may follow Heiko advice to do
some modify in dmc clock and rk3399 devfreq driver,
I will upload new version when it's ready.
>
> Cheers,
> MyungJoo
> ps. according to rk339_dmcclk_recalc_rate(), filling rk339_dmcclk_set_rate
> assuming that TZ is not enabled seems trivial.
--
Lin Huang
next prev parent reply other threads:[~2015-11-23 9:27 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-23 8:09 [PATCH 1/2] clk: rockchip: dmc: support rk3399 dmc clock driver MyungJoo Ham
2015-11-23 8:09 ` MyungJoo Ham
2015-11-23 8:09 ` MyungJoo Ham
2015-11-23 9:26 ` hl [this message]
-- strict thread matches above, loose matches on Subject: below --
2015-11-19 10:21 [PATCH 0/2] Bring up rk3399 ddr frequency scaling Lin Huang
2015-11-19 10:21 ` [PATCH 1/2] clk: rockchip: dmc: support rk3399 dmc clock driver Lin Huang
2015-11-19 21:47 ` Heiko Stuebner
2015-11-20 1:37 ` hl
2015-11-21 18:30 ` Heiko Stuebner
2015-11-23 9:20 ` hl
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