From: laura@labbott.name (Laura Abbott)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] [PATCH] arm64: Boot failure on m400 with new cont PTEs
Date: Mon, 23 Nov 2015 09:52:11 -0800 [thread overview]
Message-ID: <5653524B.40302@labbott.name> (raw)
In-Reply-To: <56534212.3000302@redhat.com>
On 11/23/15 8:42 AM, Jeremy Linton wrote:
> On 11/23/2015 10:37 AM, Laura Abbott wrote:
>> Which permissions still need to be cleaned up from your perspective?
>
> IMHO, the vast majority of the linear map should not be executable/read/write, which is what happens today.
>
With CONFIG_DEBUG_RODATA on I'm not seeing any rwx regions
# cat /sys/kernel/debug/kernel_page_tables
---[ vmalloc() Area ]---
0xffffff8000000000-0xffffff8000010000 64K RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000012000-0xffffff8000013000 4K RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000018000-0xffffff8000019000 4K RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000020000-0xffffff8000030000 64K RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000031000-0xffffff8000071000 256K RW NX SHD AF UXN MEM/NORMAL-NC
0xffffff8000080000-0xffffff8000180000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff80001ae000-0xffffff80001b1000 12K RW NX SHD AF UXN MEM/NORMAL
0xffffff8000200000-0xffffff8000300000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000380000-0xffffff8000480000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000500000-0xffffff8000600000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000680000-0xffffff8000780000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000800000-0xffffff8000900000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000980000-0xffffff8000a80000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000b00000-0xffffff8000c00000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000c80000-0xffffff8000d80000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000e00000-0xffffff8000f00000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8000f80000-0xffffff8001080000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8001100000-0xffffff8001200000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8001280000-0xffffff8001380000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8001400000-0xffffff8001500000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8001580000-0xffffff8001680000 1M RW NX SHD AF UXN DEVICE/nGnRE
0xffffff8001700000-0xffffff8001800000 1M RW NX SHD AF UXN DEVICE/nGnRE
---[ vmalloc() End ]---
---[ vmemmap start ]---
0xffffffbdc1000000-0xffffffbdc3000000 32M RW NX SHD AF BLK UXN MEM/NORMAL
---[ vmemmap end ]---
---[ Fixmap start ]---
0xffffffbffa800000-0xffffffbffaa00000 2M ro NX SHD AF BLK UXN MEM/NORMAL
---[ Fixmap end ]---
---[ PCI I/O start ]---
0xffffffbffae00000-0xffffffbffae10000 64K RW NX SHD AF UXN DEVICE/nGnRE
---[ PCI I/O end ]---
---[ Modules start ]---
---[ Modules end ]---
---[ Kernel Mapping ]---
0xffffffc000000000-0xffffffc000080000 512K RW NX SHD AF CON UXN MEM/NORMAL
0xffffffc000080000-0xffffffc000082000 8K RW NX SHD AF UXN MEM/NORMAL
0xffffffc000082000-0xffffffc000090000 56K ro x SHD AF UXN MEM/NORMAL
0xffffffc000090000-0xffffffc000200000 1472K ro x SHD AF CON UXN MEM/NORMAL
0xffffffc000200000-0xffffffc000800000 6M ro x SHD AF BLK UXN MEM/NORMAL
0xffffffc000800000-0xffffffc000980000 1536K ro x SHD AF CON UXN MEM/NORMAL
0xffffffc000980000-0xffffffc000987000 28K ro x SHD AF UXN MEM/NORMAL
0xffffffc000987000-0xffffffc000990000 36K RW NX SHD AF UXN MEM/NORMAL
0xffffffc000990000-0xffffffc000a00000 448K RW NX SHD AF CON UXN MEM/NORMAL
0xffffffc000a00000-0xffffffc000a10000 64K RW NX SHD AF UXN MEM/NORMAL
0xffffffc000a10000-0xffffffc000c00000 1984K RW NX SHD AF CON UXN MEM/NORMAL
0xffffffc000c00000-0xffffffc040000000 1012M RW NX SHD AF BLK UXN MEM/NORMAL
0xffffffc040000000-0xffffffc080000000 1G RW NX SHD AF BLK UXN MEM/NORMAL
are there other parts of the map you're seeing that aren't on my system?
Thanks,
Laura
next prev parent reply other threads:[~2015-11-23 17:52 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-18 15:03 [PATCH] [PATCH] arm64: Boot failure on m400 with new cont PTEs Jeremy Linton
2015-11-18 15:20 ` Mark Rutland
2015-11-18 16:08 ` Jeremy Linton
2015-11-18 16:29 ` Mark Rutland
2015-11-18 17:14 ` Jeremy Linton
2015-11-18 18:04 ` Mark Rutland
2015-11-18 19:31 ` Jeremy Linton
2015-11-19 11:31 ` Mark Rutland
2015-11-20 19:52 ` Mark Rutland
2015-11-23 12:15 ` Catalin Marinas
2015-11-23 13:49 ` Mark Rutland
2015-11-23 14:48 ` Jeremy Linton
2015-11-23 15:41 ` Will Deacon
2015-11-23 15:46 ` Jeremy Linton
2015-11-23 14:31 ` Jeremy Linton
2015-11-20 20:15 ` Mark Rutland
2015-11-23 15:51 ` Catalin Marinas
2015-11-23 16:02 ` Jeremy Linton
2015-11-23 16:37 ` Laura Abbott
2015-11-23 16:42 ` Jeremy Linton
2015-11-23 17:52 ` Laura Abbott [this message]
2015-11-23 18:46 ` Jeremy Linton
2015-11-24 8:04 ` Ard Biesheuvel
2015-11-23 16:52 ` Catalin Marinas
2015-11-23 17:24 ` Catalin Marinas
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