From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Mon, 23 Nov 2015 19:24:40 -0800 (PST) From: Sugar Wu To: linux-sunxi Cc: maxime.ripard@free-electrons.com, atx@atx.name, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Message-Id: <077cd975-1f91-40fe-ab05-2381e4fb6448@googlegroups.com> In-Reply-To: References: <20151123124356.GW32142@lukather> Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_7547_2088280689.1448335481093" List-ID: ------=_Part_7547_2088280689.1448335481093 Content-Type: multipart/alternative; boundary="----=_Part_7548_1988214271.1448335481094" ------=_Part_7548_1988214271.1448335481094 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable I will give you the right widths as soon. =E5=9C=A8 2015=E5=B9=B411=E6=9C=8824=E6=97=A5=E6=98=9F=E6=9C=9F=E4=BA=8C UT= C+8=E4=B8=8A=E5=8D=8811:13:41=EF=BC=8CChen-Yu Tsai=E5=86=99=E9=81=93=EF=BC= =9A > > Hi,=20 > > On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard=20 > > wrote:=20 > > Hi,=20 > >=20 > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:=20 > >> Add a node describing the Security ID memory to the=20 > >> Allwinner H3 .dtsi file.=20 > >>=20 > >> Signed-off-by: Josef Gajdusek >=20 > >> ---=20 > >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++=20 > >> 1 file changed, 7 insertions(+)=20 > >>=20 > >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi=20 > b/arch/arm/boot/dts/sun8i-h3.dtsi=20 > >> index 0faa38a..58de718 100644=20 > >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi=20 > >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi=20 > >> @@ -359,6 +359,13 @@=20 > >> #size-cells =3D <0>;=20 > >> };=20 > >>=20 > >> + sid: eeprom@01c14000 {=20 > >> + compatible =3D "allwinner,sun4i-a10-sid";=20 > >> + reg =3D <0x01c14000 0x400>;=20 > >=20 > > The datasheet says it's 256 bytes wide, while the size here is of 1kB,= =20 > > is it intentional?=20 > > My H3 datasheet (v1.1) says its 1 kB wide.=20 > > It'd be nice if Allwinner actually listed the "usable" E-fuse offsets=20 > and widths, instead of having us dig through the SDK code.=20 > > Regards=20 > ChenYu=20 > ------=_Part_7548_1988214271.1448335481094 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable
I will give you the right=C2=A0widths as soon.

=E5= =9C=A8 2015=E5=B9=B411=E6=9C=8824=E6=97=A5=E6=98=9F=E6=9C=9F=E4=BA=8C UTC+8= =E4=B8=8A=E5=8D=8811:13:41=EF=BC=8CChen-Yu Tsai=E5=86=99=E9=81=93=EF=BC=9A<= blockquote class=3D"gmail_quote" style=3D"margin: 0;margin-left: 0.8ex;bord= er-left: 1px #ccc solid;padding-left: 1ex;">Hi,

On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard
<maxime...@free-electrons.com> wrote:
> Hi,
>
> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
>> Add a node describing the Security ID memory to the
>> Allwinner H3 .dtsi file.
>>
>> Signed-off-by: Josef Gajdusek <a...@atx.name>
>> ---
>> =C2=A0arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++
>> =C2=A01 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/b= oot/dts/sun8i-h3.dtsi
>> index 0faa38a..58de718 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -359,6 +359,13 @@
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 #size-cells =3D <0>;
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 };
>>
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 sid: eeprom@01c140= 00 {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 compatible =3D "allwinner,sun4i-a10-sid";
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 reg =3D <0x01c14000 0x400>;
>
> The datasheet says it's 256 bytes wide, while the size here is= of 1kB,
> is it intentional?

My H3 datasheet (v1.1) says its 1 kB wide.

It'd be nice if Allwinner actually listed the "usable" E-= fuse offsets
and widths, instead of having us dig through the SDK code.

Regards
ChenYu
------=_Part_7548_1988214271.1448335481094-- ------=_Part_7547_2088280689.1448335481093-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Mon, 23 Nov 2015 13:43:56 +0100 From: Maxime Ripard To: Josef Gajdusek Cc: linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Message-ID: <20151123124356.GW32142@lukather> References: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="1lE8Wy7Exphh2Vpg" In-Reply-To: List-ID: --1lE8Wy7Exphh2Vpg Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > Add a node describing the Security ID memory to the > Allwinner H3 .dtsi file. >=20 > Signed-off-by: Josef Gajdusek > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) >=20 > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3= =2Edtsi > index 0faa38a..58de718 100644 > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -359,6 +359,13 @@ > #size-cells =3D <0>; > }; > =20 > + sid: eeprom@01c14000 { > + compatible =3D "allwinner,sun4i-a10-sid"; > + reg =3D <0x01c14000 0x400>; The datasheet says it's 256 bytes wide, while the size here is of 1kB, is it intentional? Thanks, Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --1lE8Wy7Exphh2Vpg Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWUwoMAAoJEBx+YmzsjxAg/6oP/2zEs+uvvg+BMHaiwjVQ0WZf 1/+uNTq4q87jl9cl2L2jsNTf+V9hZhUOI4irZ4aDR55M06pTuoCH8l8WtMqALPtQ 3UK8bHI0mgFnxooFN+QrBUOwCnNPakGy1lmDfwOUVdu4+HFgG2IDRWDEysEsBdAD WPni+DOjmFgkTxv05IgwR4e9xL+E+jzi4HR50izswRt9l/55DwxN/hE0iFsiED5y S9k1wzQ1usjw7ilMYOR6fH0UUVgMkA5p4ooedjpFRK8sIOVC2oa9SjQ7mU3FZDa+ wBP5E3aUx6wqrAYILYeSLGdLhsbGRu/fhqGbtk0FSRXPZr2HBo3umk4hFnWjeR5f JHDj9ihcPc/Ti2Mf902NPhpAkHal/fkKloipN6dz5QBHfoK56Ejnl1GWulA2zJUy BGHbAqDKGnNwWpKDOJEaUxmBZCXN1PaE8XhyPZ/ajLvRQzo4+hZjE4w4hOwSmK6A Dck0M63Hfgov8FaOrGStwMoZVB9MSYagYEnZH4Di2ubG7DBzMEdXHDvQB0HaflDg uP5zXb9Y6+81GA9joitV/QGA467YYYxnA2eZbnQ9tNK4WoR31/GnDRZgguzuhg+l uJWdDzyegheQYLt8tB7q57kTea5BRcx2HLPg6x+T4z/huLXppoPd+mCyHSfXOfte SpD+8+n6jXw3v0fk5CJA =OeCS -----END PGP SIGNATURE----- --1lE8Wy7Exphh2Vpg-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 24 Nov 2015 08:26:13 +0100 From: Maxime Ripard To: Chen-Yu Tsai Cc: Josef Gajdusek , linux-sunxi , linux-clk , linux-pm@vger.kernel.org, linux-kernel , linux-arm-kernel , devicetree , gpatchesrdh@mveas.com, Mike Turquette , Hans De Goede , Stephen Boyd , Michael Turquette , Emilio Lopez , Russell King - ARM Linux , Eduardo Valentin , Zhang Rui , Kumar Gala , Ian Campbell , Mark Rutland , Pawel Moll , Rob Herring Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Message-ID: <20151124072613.GF32142@lukather> References: <20151123124356.GW32142@lukather> <20151124063808.GB32142@lukather> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="h6w+13shfCQ8v2Yw" In-Reply-To: List-ID: --h6w+13shfCQ8v2Yw Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Nov 24, 2015 at 02:42:26PM +0800, Chen-Yu Tsai wrote: > On Tue, Nov 24, 2015 at 2:38 PM, Maxime Ripard > wrote: > > On Tue, Nov 24, 2015 at 11:13:13AM +0800, Chen-Yu Tsai wrote: > >> Hi, > >> > >> On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard > >> wrote: > >> > Hi, > >> > > >> > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > >> >> Add a node describing the Security ID memory to the > >> >> Allwinner H3 .dtsi file. > >> >> > >> >> Signed-off-by: Josef Gajdusek > >> >> --- > >> >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > >> >> 1 file changed, 7 insertions(+) > >> >> > >> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/su= n8i-h3.dtsi > >> >> index 0faa38a..58de718 100644 > >> >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi > >> >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > >> >> @@ -359,6 +359,13 @@ > >> >> #size-cells =3D <0>; > >> >> }; > >> >> > >> >> + sid: eeprom@01c14000 { > >> >> + compatible =3D "allwinner,sun4i-a10-sid"; > >> >> + reg =3D <0x01c14000 0x400>; > >> > > >> > The datasheet says it's 256 bytes wide, while the size here is of 1k= B, > >> > is it intentional? > >> > >> My H3 datasheet (v1.1) says its 1 kB wide. > > > > Is it? in the Security ID section, it is said to be 2kb =3D=3D 256B wid= e. >=20 > Right. I was looking at the memory map. Maybe it's sparsely mapped? > I guess we'll know soon. If it is just like the A20, I think there's a few registers at the end to control the writes (that we don't use). Which means that the size of the fuses is smaller than the size of the mapped area (which also measn that our driver is broken making that assumption). Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --h6w+13shfCQ8v2Yw Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWVBEVAAoJEBx+YmzsjxAg2twP/RUNC7sjVheMuZaccIeB+zTI 6KnZloJJknaDMHzFkcriZD/VEbOMU0bUG18vV7jxFvjmRSfne1MFWjurskRa33bE xZExviiYv4Asy3ap4ed3voSPmFJfF1Xzduf46ZLaJr3vfoSnQZo0+47B4j2VXsUJ afhv9mfi1I+NzKqDaEzYYC9+XM62OO9W7HfghBjYiBSfArwUtW6Tfka/EixENeHF B1iHJ7u6GBEZerIlbBNjTLYbrQp7XgwUCT86Oy+ndy3E05R65t518U/mMNc8K4nu 33K9ye8u8NhGFFOpLSbGJlsKl+vkfPMz8vH0VKz+YW5JAfc8fKpBVTt1WIuMfeaw yKP/uDd+8Jodhr6box4T96UonSOG1U9cUR+JoB8RvBif6JfQfnJwZyiQHG6lU1Ai Q5DY+VUAz6WD0m75rl3pegrxyHgydqOKPN46UKCRks22yH4f+OkOSW1z8hG/lwsm Fjr2eKEWtRTRFFzQckHPFTHvTFKTSWeUE0xoftN63cWO2H03xxT1psUZjwOd0wDd bCZCoJSO+4rx/AtR2FwS5Hn9cVuOQghKyCWWTqI0H/Rm2c99QWUMVE8AFtG1IhKV NbLIPWjykhX1AfutR0/lJ78BJGnrXHFC8LPOlzlmVJTZ19mj1FxqFyc977sUEi+W DHiRqGan93fOcWh0v8vM =Db5t -----END PGP SIGNATURE----- --h6w+13shfCQ8v2Yw-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 24 Nov 2015 07:38:30 +0100 From: Maxime Ripard To: Sugar Wu Cc: linux-sunxi , atx@atx.name, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Message-ID: <20151124063830.GC32142@lukather> References: <20151123124356.GW32142@lukather> <077cd975-1f91-40fe-ab05-2381e4fb6448@googlegroups.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="UIrAl4r1g2eOkvhC" In-Reply-To: <077cd975-1f91-40fe-ab05-2381e4fb6448@googlegroups.com> List-ID: --UIrAl4r1g2eOkvhC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Nov 23, 2015 at 07:24:40PM -0800, Sugar Wu wrote: > I will give you the right widths as soon. Great, thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --UIrAl4r1g2eOkvhC Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWVAXmAAoJEBx+YmzsjxAgU00QAKwDlOYfD+z261U4DzioUauj UTHijG/ParXTaQ7w6oACzqFHqHi4gCz38X21ZL/1T+7NSsXz2hUXxKk6RGZcq5Ii KO4ngp8o2WLhawzd/oApAJiZPpTXkINsQ0g405gKRrHDrWMz0bY/cj09vjxX3UtT JAuM5HGNcdu0E16luVZs3fc7hzYhTS6sAtAbWHpRnYwX6bcOKiRqnwi1UdVrg+CQ y/krF3lBuY9XEgUssf2nx6PzVh/aQjcvEeC33UuaSoU5MBe1/a85itFhegCJRgzm pMpmfnw4Zh4dT8R20lM7MzypuixEVnkVKBsqd9BBSHM4GCcs50hw3kSvsPQRSWkQ ANT55OMWSspApHhlFsorH6RXPRPT1FkGuTPhOgoRNxcC8vjSWs75fVPo6PMbUffp BkLA8cBwY+NO4oMQrePmRqc7Z+GRLnNRNqGO2Da9ja6SwXYJxV0N2enoGOqa/I0S 5jnuEpHBd2JL2XQOddsFdSor3OEeUQ9DB1XQ3wmvJj8QIzc/Jc9rsk8fJl7fBiPW Js2kQiND1EWNy4EwQZPzekBYKNNuO+UNYSZRFDwFbaJ/ImPck7Dxihr1ZlvPLjhX gfw+pRsuG/kx4GHHVeAUGM5gv0X478px5w7EwZqmcOcCh9JxauHCjuwqcVTjVoTr lOPpMJOunEl2hEKYjY8i =SdKB -----END PGP SIGNATURE----- --UIrAl4r1g2eOkvhC-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 24 Nov 2015 09:45:31 +0100 From: Maxime Ripard To: Josef Gajdusek Cc: linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: Re: [PATCH v2 5/5] ARM: dts: sun8i: Add THS node to the H3 .dtsi Message-ID: <20151124084531.GK32142@lukather> References: <0fff612e26bf9cda9027a4175e16d25a0c2cc62c.1448263428.git.atx@atx.name> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="1QzJaSEX5hKRjM1z" In-Reply-To: <0fff612e26bf9cda9027a4175e16d25a0c2cc62c.1448263428.git.atx@atx.name> List-ID: --1QzJaSEX5hKRjM1z Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Nov 23, 2015 at 09:02:52AM +0100, Josef Gajdusek wrote: > + ths: ths@01c25000 { > + #thermal-sensor-cells =3D <0>; > + compatible =3D "allwinner,sun8i-h3-ths"; > + reg =3D <0x01c25000 0x88>; The datasheet says the size is 0x400, any particular reason to have a Thanks, Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --1QzJaSEX5hKRjM1z Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWVCOrAAoJEBx+YmzsjxAgHn8P/RNoAmuUKvT34eXQ5cFmz8cd LS1DDrfvGkdHC9aOL92B8TSnyetBOS68tI3eLkW2sgagi1qbj0o1snjf73P8nFCc eTGSYT6J4ewmaPuPfnEOYidGHYpk1rfoUfvyDr6WtbKZvdiZV718LFsF0m+wPJTG Qi8WiYIkfdwHRfnxiuaCeGJ1dbKF2pXtP3aGc3EkiBP7hFfaoXcl4KFyc0+qUvTw 1aWxBkV8EawfdK4I5C3OnCB/8bPZb8bsmlMhPydca23SnYBT4wYcT+oRrlOpdvmj FuXqVSBw1agDZ7t2XaxW0rvJdB0HqAUx9yZNJqA+3AlCSQXQ+NfUSZi1mkd7z1R4 X6yIDCI82WdoJcOtrkIgd+emATYZVjvrmNU7CH+O0YFYUKG4TWRJqk+FSmu89C4i ZXjoLruE4sOmGZDyUM/PAcKnBpTdWnQd2IvHyar5KUsKy6GB5xm+UrWLN4jJUMW6 e/B4dgEYkvUunRorQ5JuXHDur79CJieHQ85cOZ8zf/JZ8b4JJRtXyJORCSmZ7chy 57DADYWMi8+X48cYtKfT80S/Be6KOIcNvmDWsVUobclwy9PElifJj+UBnDOmqK47 qHB+21HHqkD5dvaZS0ragyeN4XZqqz055KjA1SswI6oZ855Zr2I83UXFOkLOQodQ 9EuPNWhW5r4/a0VyjRpi =f4uw -----END PGP SIGNATURE----- --1QzJaSEX5hKRjM1z-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Josef Gajdusek To: linux-sunxi@googlegroups.com Cc: Josef Gajdusek , linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, maxime.ripard@free-electrons.com, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: [PATCH v2 5/5] ARM: dts: sun8i: Add THS node to the H3 .dtsi Date: Mon, 23 Nov 2015 09:02:52 +0100 Message-Id: <0fff612e26bf9cda9027a4175e16d25a0c2cc62c.1448263428.git.atx@atx.name> In-Reply-To: References: In-Reply-To: References: List-ID: This patch adds nodes for the THS driver and the THS clock to the Allwinner H3 .dtsi file. Signed-off-by: Josef Gajdusek --- arch/arm/boot/dts/sun8i-h3.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 58de718..48500d4 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -77,6 +77,14 @@ }; }; + thermal-zones { + cpu_thermal: cpu_thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 0>; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -236,6 +244,14 @@ "ahb1_ephy", "ahb1_dbg"; }; + ths_clk: clk@01c20074 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ths-clk"; + reg = <0x01c20074 0x4>; + clocks = <&osc24M>; + clock-output-names = "ths"; + }; + mmc0_clk: clk@01c20088 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; @@ -364,6 +380,10 @@ reg = <0x01c14000 0x400>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: calib@234 { + reg = <0x234 0x4>; + }; }; usbphy: phy@01c19400 { @@ -529,6 +549,19 @@ interrupts = ; }; + ths: ths@01c25000 { + #thermal-sensor-cells = <0>; + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x88>; + interrupts = ; + resets = <&bus_rst 104>; + reset-names = "ahb"; + clocks = <&bus_gates 72>, <&ths_clk>; + clock-names = "ahb", "ths"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 24 Nov 2015 09:43:42 +0100 From: Maxime Ripard To: Josef Gajdusek Cc: linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: Re: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor Message-ID: <20151124084342.GJ32142@lukather> References: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="bBvR1PRdT0lNhZQk" In-Reply-To: List-ID: --bBvR1PRdT0lNhZQk Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Nov 23, 2015 at 09:02:50AM +0100, Josef Gajdusek wrote: > This patch adds support for the Sunxi thermal sensor on the Allwinner H3. You can drop the sunxi here. > Should be easily extendable for the A33/A83T/... as they have similar but > not completely identical sensors. >=20 > Signed-off-by: Josef Gajdusek > --- > drivers/thermal/Kconfig | 7 + > drivers/thermal/Makefile | 1 + > drivers/thermal/sun8i_ths.c | 365 ++++++++++++++++++++++++++++++++++++++= ++++++ > 3 files changed, 373 insertions(+) > create mode 100644 drivers/thermal/sun8i_ths.c >=20 > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index c463c89..2b41147 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > =20 > +config SUN8I_THS > + tristate "sun8i THS driver" > + depends on MACH_SUN8I > + depends on OF > + help > + Enable this to support thermal reporting on some newer Allwinner SoCs. > + > menu "Texas Instruments thermal drivers" > depends on ARCH_HAS_BANDGAP || COMPILE_TEST > source "drivers/thermal/ti-soc-thermal/Kconfig" > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index cfae6a6..227e1a1 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) +=3D intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) +=3D st/ > obj-$(CONFIG_TEGRA_SOCTHERM) +=3D tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) +=3D hisi_thermal.o > +obj-$(CONFIG_SUN8I_THS) +=3D sun8i_ths.o > diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c > new file mode 100644 > index 0000000..2c976ac > --- /dev/null > +++ b/drivers/thermal/sun8i_ths.c > @@ -0,0 +1,365 @@ > +/* > + * Sunxi THS driver sun8i Thermal Sensor Driver > + * Copyright (C) 2015 Josef Gajdusek > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include Are you using this header? > +#include > +#include > +#include You probably don't need this one too. > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define THS_H3_CTRL0 0x00 > +#define THS_H3_CTRL1 0x04 > +#define THS_H3_CDAT 0x14 > +#define THS_H3_CTRL2 0x40 > +#define THS_H3_INT_CTRL 0x44 > +#define THS_H3_STAT 0x48 > +#define THS_H3_ALARM_CTRL 0x50 > +#define THS_H3_SHUTDOWN_CTRL 0x60 > +#define THS_H3_FILTER 0x70 > +#define THS_H3_CDATA 0x74 > +#define THS_H3_DATA 0x80 > + > +#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS 0 > +#define THS_H3_CTRL0_SENSOR_ACQ0(x) \ > + ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS) > +#define THS_H3_CTRL1_ADC_CALI_EN_OFFS 17 > +#define THS_H3_CTRL1_ADC_CALI_EN \ > + BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS) > +#define THS_H3_CTRL1_OP_BIAS_OFFS 20 > +#define THS_H3_CTRL1_OP_BIAS(x) \ > + ((x) << THS_H3_CTRL1_OP_BIAS_OFFS) > +#define THS_H3_CTRL2_SENSE_EN_OFFS 0 > +#define THS_H3_CTRL2_SENSE_EN \ > + BIT(THS_H3_CTRL2_SENSE_EN_OFFS) > +#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS 16 > +#define THS_H3_CTRL2_SENSOR_ACQ1(x) \ > + ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS) > + > +#define THS_H3_INT_CTRL_ALARM_INT_EN_OFFS 0 > +#define THS_H3_INT_CTRL_ALARM_INT_EN \ > + BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS) > +#define THS_H3_INT_CTRL_SHUT_INT_EN_OFFS 4 > +#define THS_H3_INT_CTRL_SHUT_INT_EN \ > + BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS) > +#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS 8 > +#define THS_H3_INT_CTRL_DATA_IRQ_EN \ > + BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS) > +#define THS_H3_INT_CTRL_THERMAL_PER_OFFS 12 > +#define THS_H3_INT_CTRL_THERMAL_PER(x) \ > + ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS) > + > +#define THS_H3_STAT_ALARM_INT_STS_OFFS 0 > +#define THS_H3_STAT_ALARM_INT_STS \ > + BIT(THS_H3_STAT_ALARM_INT_STS_OFFS) > +#define THS_H3_STAT_SHUT_INT_STS_OFFS 4 > +#define THS_H3_STAT_SHUT_INT_STS \ > + BIT(THS_H3_STAT_SHUT_INT_STS_OFFS) > +#define THS_H3_STAT_DATA_IRQ_STS_OFFS 8 > +#define THS_H3_STAT_DATA_IRQ_STS \ > + BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS) > +#define THS_H3_STAT_ALARM_OFF_STS_OFFS 12 > +#define THS_H3_STAT_ALARM_OFF_STS \ > + BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS) > + > +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS 0 > +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST(x) \ > + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS) > +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS 16 > +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT(x) \ > + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS) > + > +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS 16 > +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT(x) \ > + ((x) << THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS) > + > +#define THS_H3_FILTER_TYPE_OFFS 0 > +#define THS_H3_FILTER_TYPE(x) \ > + ((x) << THS_H3_FILTER_TYPE_OFFS) > +#define THS_H3_FILTER_EN_OFFS 2 > +#define THS_H3_FILTER_EN \ > + BIT(THS_H3_FILTER_EN_OFFS) Are you using these offsets anywhere? > + > +#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0xff > +#define THS_H3_INT_CTRL_THERMAL_PER_VALUE 0x79 > +#define THS_H3_FILTER_TYPE_VALUE 0x2 > +#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f > + > +struct sun8i_ths_data { > + struct sun8i_ths_type *type; > + struct reset_control *reset; > + struct clk *clk; > + struct clk *busclk; > + void __iomem *regs; > + struct nvmem_cell *calcell; > + struct platform_device *pdev; > + struct thermal_zone_device *tzd; > +}; > + > +struct sun8i_ths_type { > + int (*init)(struct platform_device *, struct sun8i_ths_data *); > + int (*get_temp)(struct sun8i_ths_data *, int *out); > + void (*irq)(struct sun8i_ths_data *); > + void (*deinit)(struct sun8i_ths_data *); > +}; AFAIK, you never got back on why it was actually needed, instead of directly calling these functions. > +/* Formula and parameters from the Allwinner 3.4 kernel */ > +static int sun8i_ths_reg_to_temperature(s32 reg, int divisor, int consta= nt) > +{ > + return constant - (reg * 1000000) / divisor; > +} > + > +static int sun8i_ths_get_temp(void *_data, int *out) > +{ > + struct sun8i_ths_data *data =3D _data; > + > + return data->type->get_temp(data, out); > +} > + > +static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data) > +{ > + struct sun8i_ths_data *data =3D _data; > + > + data->type->irq(data); > + thermal_zone_device_update(data->tzd); > + > + return IRQ_HANDLED; > +} > + > +static int sun8i_ths_h3_init(struct platform_device *pdev, > + struct sun8i_ths_data *data) > +{ > + int ret; > + size_t callen; > + s32 *caldata; > + > + data->busclk =3D devm_clk_get(&pdev->dev, "ahb"); > + if (IS_ERR(data->busclk)) { > + ret =3D PTR_ERR(data->busclk); > + dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret); > + return ret; > + } > + > + data->clk =3D devm_clk_get(&pdev->dev, "ths"); > + if (IS_ERR(data->clk)) { > + ret =3D PTR_ERR(data->clk); > + dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret); > + return ret; > + } > + > + data->reset =3D devm_reset_control_get(&pdev->dev, "ahb"); > + if (IS_ERR(data->reset)) { > + ret =3D PTR_ERR(data->reset); > + dev_err(&pdev->dev, "failed to get reset: %d\n", ret); > + return ret; > + } > + > + if (data->calcell) { > + caldata =3D nvmem_cell_read(data->calcell, &callen); > + if (IS_ERR(caldata)) > + return PTR_ERR(caldata); > + writel(be32_to_cpu(*caldata), data->regs + THS_H3_CDATA); > + kfree(caldata); > + } > + > + ret =3D clk_prepare_enable(data->busclk); > + if (ret) { > + dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret); > + return ret; > + } > + > + ret =3D clk_prepare_enable(data->clk); > + if (ret) { > + dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret); > + goto err_disable_bus; > + } > + > + ret =3D reset_control_deassert(data->reset); > + if (ret) { > + dev_err(&pdev->dev, "reset deassert failed: %d\n", ret); > + goto err_disable_ths; > + } > + > + /* The final sample period is calculated as follows: > + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) > + * > + * This results to about 1Hz with these settings. > + */ > + ret =3D clk_set_rate(data->clk, 4000000); I don't follow you here. You have a complicated math function, that has many input variables, and then, you just set the clock rate to a constant? > + if (ret) > + goto err_disable_ths; A new line here please > + writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE), > + data->regs + THS_H3_CTRL0); > + writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) | > + THS_H3_INT_CTRL_DATA_IRQ_EN, > + data->regs + THS_H3_INT_CTRL); > + writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE), > + data->regs + THS_H3_FILTER); > + writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) | > + THS_H3_CTRL2_SENSE_EN, > + data->regs + THS_H3_CTRL2); And here too. > + return 0; > + > +err_disable_ths: > + clk_disable_unprepare(data->clk); > +err_disable_bus: > + clk_disable_unprepare(data->busclk); > + > + return ret; > +} > + > +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *out) > +{ > + int val =3D readl(data->regs + THS_H3_DATA); > + *out =3D sun8i_ths_reg_to_temperature(val, 8253, 217000); > + return 0; Can't you just return the value directly? > +} > + > +static void sun8i_ths_h3_irq(struct sun8i_ths_data *data) > +{ > + writel(THS_H3_STAT_DATA_IRQ_STS | > + THS_H3_STAT_ALARM_INT_STS | > + THS_H3_STAT_ALARM_OFF_STS | > + THS_H3_STAT_SHUT_INT_STS, > + data->regs + THS_H3_STAT); So you're always clearing all the interrupts? Shouldn't you just clear only the interrupt you received? > +} > + > +static void sun8i_ths_h3_deinit(struct sun8i_ths_data *data) > +{ > + reset_control_assert(data->reset); > + clk_disable_unprepare(data->clk); > + clk_disable_unprepare(data->busclk); > +} > + > +static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops =3D= { > + .get_temp =3D sun8i_ths_get_temp, > +}; > + > +static const struct sun8i_ths_type sun8i_ths_device_h3 =3D { > + .init =3D sun8i_ths_h3_init, > + .get_temp =3D sun8i_ths_h3_get_temp, > + .irq =3D sun8i_ths_h3_irq, > + .deinit =3D sun8i_ths_h3_deinit, > +}; > + > +static const struct of_device_id sun8i_ths_id_table[] =3D { > + { > + .compatible =3D "allwinner,sun8i-h3-ths", > + .data =3D &sun8i_ths_device_h3, > + }, > + { > + /* sentinel */ > + }, > +}; > +MODULE_DEVICE_TABLE(of, sun8i_ths_id_table); > + > +static int sun8i_ths_probe(struct platform_device *pdev) > +{ > + struct device_node *np =3D pdev->dev.of_node; > + const struct of_device_id *match; > + struct sun8i_ths_data *data; > + struct resource *res; > + int ret; > + int irq; > + > + match =3D of_match_node(sun8i_ths_id_table, np); If you *really* need to (but I still don't really see why), you can use of_device_get_match_data here. > + > + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + data->type =3D (struct sun8i_ths_type *)match->data; > + data->pdev =3D pdev; > + > + data->calcell =3D devm_nvmem_cell_get(&pdev->dev, "calibration"); > + if (IS_ERR(data->calcell)) { > + if (PTR_ERR(data->calcell) =3D=3D -EPROBE_DEFER) > + return PTR_ERR(data->calcell); New line > + data->calcell =3D NULL; /* No calibration register */ s/register/data/ ? > + } > + > + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > + data->regs =3D devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(data->regs)) { > + ret =3D PTR_ERR(data->regs); > + dev_err(&pdev->dev, > + "failed to ioremap THS registers: %d\n", ret); > + return ret; > + } > + > + irq =3D platform_get_irq(pdev, 0); > + if (irq < 0) { > + dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); > + return irq; > + } > + > + ret =3D devm_request_threaded_irq(&pdev->dev, irq, NULL, > + sun8i_ths_irq_thread, IRQF_ONESHOT, > + dev_name(&pdev->dev), data); Why a threaded irq? > + if (ret) > + return ret; > + > + ret =3D data->type->init(pdev, data); > + if (ret) > + return ret; > + > + data->tzd =3D thermal_zone_of_sensor_register(&pdev->dev, 0, data, > + &sun8i_ths_thermal_ops); > + if (IS_ERR(data->tzd)) { > + ret =3D PTR_ERR(data->tzd); > + dev_err(&pdev->dev, "failed to register thermal zone: %d\n", > + ret); > + goto err_deinit; > + } > + > + platform_set_drvdata(pdev, data); > + return 0; > + > +err_deinit: > + data->type->deinit(data); > + return ret; > +} > + > +static int sun8i_ths_remove(struct platform_device *pdev) > +{ > + struct sun8i_ths_data *data =3D platform_get_drvdata(pdev); > + > + thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); > + data->type->deinit(data); > + return 0; > +} > + > +static struct platform_driver sun8i_ths_driver =3D { > + .probe =3D sun8i_ths_probe, > + .remove =3D sun8i_ths_remove, > + .driver =3D { > + .name =3D "sun8i_ths", > + .of_match_table =3D sun8i_ths_id_table, > + }, > +}; > + > +module_platform_driver(sun8i_ths_driver); > + > +MODULE_AUTHOR("Josef Gajdusek "); > +MODULE_DESCRIPTION("Sunxi THS driver"); Please change the description here too to match the header. Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --bBvR1PRdT0lNhZQk Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWVCM+AAoJEBx+YmzsjxAgsfAP/iQft6kRAa8ckddDKd4FC7Cs xE34QW6WmN84Q+rMGdFOAzKkNkBp0KHyFwZB9oaPL2p998UMExK3xMi26irm8haJ Vgi1uEK4070l/8jejBgq8ee1qq8cJwc7M3axcxwJCT/ECmfq69pt9Ke78VmHs/vt vBkJlEJ5DbkxfsRdTaONh81HIx9+sqZSX/XLDUxWr4LIrgY2XKE3cPRyKZYZzCva 80yAoSDOMSn3WW498PcrgHy3UmnLwlP8wnIIPJywU9r88D1qvY5qRL87HRnfu2Ef FOltGZu/neJMvWJQr5WDqp8+fFUyUuld3AkRh1uXfU7Q4MuEopBiH+q++2mBSXTh gzZH4w/VOFY9EzD6NB59i6m/QHhbdKDpDIZJt2y1VDBAYbrm1Ka8lO2uxN/0mzfn hKmZx/TNuWaAYJVuHcqk9Tdz2AywEbKuN8X9ADpYH8QRrKPSZHfIYRURMhxUOx0Q FPHfM1JjVVSnMG8kNjYHFs4dHKojFI+cLHPFxEaNjYahPJcfVVHT5gFCEGmlJTdu OjKuSxxCgnjYijMtq++8IZWFT1OyYDZpLsONvlBkL/goWJcCu99swhguvwvgFYK6 8gSr7OBu7VSq7OvWKdoKXJQ2YF8PZEZImvQ3uTe9PUWv5HF0D1nbTnqAEsGvUWGQ YZQxLnAIEwsgqS+F/MO7 =AKPh -----END PGP SIGNATURE----- --bBvR1PRdT0lNhZQk-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Mon, 23 Nov 2015 15:37:08 -0600 From: Rob Herring To: Josef Gajdusek Cc: linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, maxime.ripard@free-electrons.com, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com Subject: Re: [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock Message-ID: <20151123213708.GA12308@rob-hp-laptop> References: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> List-ID: On Mon, Nov 23, 2015 at 09:02:49AM +0100, Josef Gajdusek wrote: > This patch adds a driver for the THS clock which is present on the > Allwinner H3. > > Signed-off-by: Josef Gajdusek Acked-by: Rob Herring > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk-h3-ths.c | 98 +++++++++++++++++++++++ > 3 files changed, 100 insertions(+) > create mode 100644 drivers/clk/sunxi/clk-h3-ths.c > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > index 23e7bce..6d63b35 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -73,6 +73,7 @@ Required properties: > "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 > "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 > "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 > + "allwinner,sun8i-h3-ths-clk" - for THS on H3 > > Required properties for all clocks: > - reg : shall be the control register address for the clock. > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index f520af6..1bf8e1c 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -8,6 +8,7 @@ obj-y += clk-a10-hosc.o > obj-y += clk-a10-mod1.o > obj-y += clk-a10-pll2.o > obj-y += clk-a20-gmac.o > +obj-y += clk-h3-ths.o > obj-y += clk-mod0.o > obj-y += clk-simple-gates.o > obj-y += clk-sun8i-bus-gates.o > diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk-h3-ths.c > new file mode 100644 > index 0000000..663afc0 > --- /dev/null > +++ b/drivers/clk/sunxi/clk-h3-ths.c > @@ -0,0 +1,98 @@ > +/* > + * Sunxi THS clock driver > + * > + * Copyright (C) 2015 Josef Gajdusek > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > + > +#define SUN8I_H3_THS_CLK_ENABLE 31 > +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0 > +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2 > + > +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock); > + > +static const struct clk_div_table sun8i_h3_ths_clk_table[] __initconst = { > + { .val = 0, .div = 1 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 6 }, > + { } /* sentinel */ > +}; > + > +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) > +{ > + struct clk *clk; > + struct clk_gate *gate; > + struct clk_divider *div; > + const char *parent; > + const char *clk_name = node->name; > + void __iomem *reg; > + int err; > + > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > + > + if (IS_ERR(reg)) > + return; > + > + gate = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!gate) > + goto err_unmap; > + > + div = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!div) > + goto err_gate_free; > + > + of_property_read_string(node, "clock-output-names", &clk_name); > + parent = of_clk_get_parent_name(node, 0); > + > + gate->reg = reg; > + gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE; > + gate->lock = &sun8i_h3_ths_clk_lock; > + > + div->reg = reg; > + div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT; > + div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH; > + div->table = sun8i_h3_ths_clk_table; > + div->lock = &sun8i_h3_ths_clk_lock; > + > + clk = clk_register_composite(NULL, clk_name, &parent, 1, > + NULL, NULL, > + &div->hw, &clk_divider_ops, > + &gate->hw, &clk_gate_ops, > + CLK_SET_RATE_PARENT); > + > + if (IS_ERR(clk)) > + goto err_div_free; > + > + err = of_clk_add_provider(node, of_clk_src_simple_get, clk); > + if (err) > + goto err_unregister_clk; > + > + return; > + > +err_unregister_clk: > + clk_unregister(clk); > +err_gate_free: > + kfree(gate); > +err_div_free: > + kfree(div); > +err_unmap: > + iounmap(reg); > +} > + > +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk", > + sun8i_h3_ths_clk_setup); > -- > 2.4.10 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Josef Gajdusek To: linux-sunxi@googlegroups.com Cc: Josef Gajdusek , linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, maxime.ripard@free-electrons.com, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: [PATCH v2 4/5] dt-bindings: document sun8i_ths Date: Mon, 23 Nov 2015 09:02:51 +0100 Message-Id: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> In-Reply-To: References: In-Reply-To: References: List-ID: This patch adds the binding documentation for the sun8i_ths driver Signed-off-by: Josef Gajdusek --- .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt new file mode 100644 index 0000000..67056bf --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt @@ -0,0 +1,31 @@ +* sun8i THS + +Required properties: +- compatible : "allwinner,sun8i-h3-ths" +- reg : Address range of the thermal registers and location of the calibration + value +- resets : Must contain an entry for each entry in reset-names. + see ../reset/reset.txt for details +- reset-names : Must include the name "ahb" +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS + clock + +Optional properties: +- nvmem-cells : Must contain an entry for each entry in nvmem-cell-names +- nvmem-cell-names : Must contain "calibration" for the cell containing the + temperature calibration cell, if available + +Example: +ths: ths@01c25000 { + #thermal-sensor-cells = <0>; + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x88>, <0x01c14234 0x4>; + interrupts = ; + resets = <&bus_rst 136>; + reset-names = "ahb"; + clocks = <&bus_gates 72>, <&ths_clk>; + clock-names = "ahb", "ths"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; +}; -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Mon, 23 Nov 2015 22:51:15 -0800 (PST) From: Sugar Wu To: linux-sunxi Cc: atx@atx.name, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Message-Id: In-Reply-To: <20151123124356.GW32142@lukather> References: <20151123124356.GW32142@lukather> Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_7799_1307141804.1448347875675" List-ID: ------=_Part_7799_1307141804.1448347875675 Content-Type: multipart/alternative; boundary="----=_Part_7800_1893462329.1448347875675" ------=_Part_7800_1893462329.1448347875675 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: > > Hi, > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > > Add a node describing the Security ID memory to the > > Allwinner H3 .dtsi file. > > > > Signed-off-by: Josef Gajdusek > > > --- > > arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi > b/arch/arm/boot/dts/sun8i-h3.dtsi > > index 0faa38a..58de718 100644 > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > > @@ -359,6 +359,13 @@ > > #size-cells = <0>; > > }; > > > > + sid: eeprom@01c14000 { > > + compatible = "allwinner,sun4i-a10-sid"; > > + reg = <0x01c14000 0x400>; > > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > is it intentional? SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space. H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. > > Thanks, > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com > ------=_Part_7800_1893462329.1448347875675 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable

On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wro= te:
Hi,

On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
> Add a node describing the Security ID memory to the
> Allwinner H3 .dtsi file.
>=20
> Signed-off-by: Josef Gajdusek <a...@atx.name>
> ---
> =C2=A0arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++
> =C2=A01 file changed, 7 insertions(+)
>=20
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/= dts/sun8i-h3.dtsi
> index 0faa38a..58de718 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -359,6 +359,13 @@
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0#size-cells =3D <0>;
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0};
> =C2=A0
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0sid: eeprom@01c14000 {
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0compatible =3D "allwinner,sun4i-a10-sid";
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0reg =3D <0x01c14000 0x400>;

The datasheet says it's 256 bytes wide, while the size here is of 1= kB,
is it intentional?
SID memory map is 0x01c14000 ~ 0x0= 1c143FF, include 2048bits efuse space.
H3 efuse space is SID_SRAM= , its range is =C2=A00x01c14200 ~ +0x100.
=C2=A0
Thanks,
Maxime

--=20
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.c= om
------=_Part_7800_1893462329.1448347875675-- ------=_Part_7799_1307141804.1448347875675-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Mon, 23 Nov 2015 13:38:37 +0100 From: Maxime Ripard To: Josef Gajdusek Cc: linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: Re: [PATCH v2 4/5] dt-bindings: document sun8i_ths Message-ID: <20151123123837.GV32142@lukather> References: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Fh5LqGQwq8YwuKb/" In-Reply-To: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> List-ID: --Fh5LqGQwq8YwuKb/ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Mon, Nov 23, 2015 at 09:02:51AM +0100, Josef Gajdusek wrote: > This patch adds the binding documentation for the sun8i_ths driver >=20 > Signed-off-by: Josef Gajdusek > --- > .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++++++++++++++++= ++++++ > 1 file changed, 31 insertions(+) > create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.t= xt >=20 > diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Do= cumentation/devicetree/bindings/thermal/sun8i-ths.txt > new file mode 100644 > index 0000000..67056bf > --- /dev/null > +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > @@ -0,0 +1,31 @@ > +* sun8i THS > + > +Required properties: > +- compatible : "allwinner,sun8i-h3-ths" > +- reg : Address range of the thermal registers and location of the calib= ration > + value > +- resets : Must contain an entry for each entry in reset-names. > + see ../reset/reset.txt for details > +- reset-names : Must include the name "ahb" If you have a single reset line, you don't need reset-names. Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --Fh5LqGQwq8YwuKb/ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWUwjNAAoJEBx+YmzsjxAg7RQQAKw7zTmUQW0gQ8sKDwxfAHgh NwZ9SfCJhICnK5Q4r2/YdXXEq/lqHV+rFCM+jRnCRl83M7C1OnKAmH9GVmkYXzbE EIadUEcrMvO6iqzNUcnoKzT0nfBcX+JxjIMB5tg0JtXN/cakxEnigd/uRdTh4far F2RQzoGOx6Myeu6xmTsDzxcz4UfwgbM85lpXvwScvdLGHzedbjRk3firSiA+Z5xY +bOTQoUq5qL1MRWbthkjkgVP/Naw884ZPIcYlvRdZ+KYFPS6UVkl87/AJgvR+ko0 RmF3wk82WKFnjYUeqOSZfZpV9+iRJlTc2hH8jQ16hREYNcSdwNll/03QsOCurQ76 hgagbqEe7M8mlFtLFkxG0THdHdXBqvaEF9IThr/JvY8r4dJOwt0EzT/jHHNms7Ew mfl+cnZS7Hz+DMYlUyV0hCTZIsyt4LQGsbfx35yaHprn9OB/JEAspPN7VAaSH8i6 bPLo7A73ihHXcoAFA94NnYLFmEBAfVGLM4u6kxW37iglf1v9fnHILdZyaNVV9fq7 HeZWvvUuot9lWhMAFznNefksHlLZtvNAglDGoDoCRFm9QMsepvPsJLOiHwPkofAO WH8/10p4KkHzhB+gdEn5okfG51d0ZJVuN5f3+Wew0Jhsy/66P3Y8pm3k0atSjfqH 5Sg13VLPGBl9z+UpBurs =75IQ -----END PGP SIGNATURE----- --Fh5LqGQwq8YwuKb/-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 In-Reply-To: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> References: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> From: Chen-Yu Tsai Date: Mon, 23 Nov 2015 17:47:11 +0800 Message-ID: Subject: Re: [PATCH v2 4/5] dt-bindings: document sun8i_ths To: Josef Gajdusek Cc: linux-sunxi , linux-clk , linux-pm@vger.kernel.org, linux-kernel , linux-arm-kernel , devicetree , gpatchesrdh@mveas.com, Mike Turquette , Hans De Goede , Stephen Boyd , Michael Turquette , Emilio Lopez , Russell King - ARM Linux , Eduardo Valentin , Zhang Rui , Chen-Yu Tsai , Maxime Ripard , Kumar Gala , Ian Campbell , Mark Rutland , Pawel Moll , Rob Herring Content-Type: text/plain; charset=UTF-8 List-ID: On Mon, Nov 23, 2015 at 4:02 PM, Josef Gajdusek wrote: > This patch adds the binding documentation for the sun8i_ths driver > > Signed-off-by: Josef Gajdusek > --- > .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt > > diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > new file mode 100644 > index 0000000..67056bf > --- /dev/null > +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > @@ -0,0 +1,31 @@ > +* sun8i THS > + > +Required properties: > +- compatible : "allwinner,sun8i-h3-ths" > +- reg : Address range of the thermal registers and location of the calibration > + value You are now using nvmem for the calibration data. You don't need the second entry. > +- resets : Must contain an entry for each entry in reset-names. > + see ../reset/reset.txt for details > +- reset-names : Must include the name "ahb" > +- clocks : Must contain an entry for each entry in clock-names. > +- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS > + clock > + > +Optional properties: > +- nvmem-cells : Must contain an entry for each entry in nvmem-cell-names > +- nvmem-cell-names : Must contain "calibration" for the cell containing the > + temperature calibration cell, if available > + > +Example: > +ths: ths@01c25000 { > + #thermal-sensor-cells = <0>; > + compatible = "allwinner,sun8i-h3-ths"; > + reg = <0x01c25000 0x88>, <0x01c14234 0x4>; Same here. ChenYu > + interrupts = ; > + resets = <&bus_rst 136>; > + reset-names = "ahb"; > + clocks = <&bus_gates 72>, <&ths_clk>; > + clock-names = "ahb", "ths"; > + nvmem-cells = <&ths_calibration>; > + nvmem-cell-names = "calibration"; > +}; > -- > 2.4.10 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 In-Reply-To: <20151124063808.GB32142@lukather> References: <20151123124356.GW32142@lukather> <20151124063808.GB32142@lukather> From: Chen-Yu Tsai Date: Tue, 24 Nov 2015 14:42:26 +0800 Message-ID: Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node To: Maxime Ripard Cc: Chen-Yu Tsai , Josef Gajdusek , linux-sunxi , linux-clk , linux-pm@vger.kernel.org, linux-kernel , linux-arm-kernel , devicetree , gpatchesrdh@mveas.com, Mike Turquette , Hans De Goede , Stephen Boyd , Michael Turquette , Emilio Lopez , Russell King - ARM Linux , Eduardo Valentin , Zhang Rui , Kumar Gala , Ian Campbell , Mark Rutland , Pawel Moll , Rob Herring Content-Type: text/plain; charset=UTF-8 List-ID: On Tue, Nov 24, 2015 at 2:38 PM, Maxime Ripard wrote: > On Tue, Nov 24, 2015 at 11:13:13AM +0800, Chen-Yu Tsai wrote: >> Hi, >> >> On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard >> wrote: >> > Hi, >> > >> > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: >> >> Add a node describing the Security ID memory to the >> >> Allwinner H3 .dtsi file. >> >> >> >> Signed-off-by: Josef Gajdusek >> >> --- >> >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ >> >> 1 file changed, 7 insertions(+) >> >> >> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi >> >> index 0faa38a..58de718 100644 >> >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi >> >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >> >> @@ -359,6 +359,13 @@ >> >> #size-cells = <0>; >> >> }; >> >> >> >> + sid: eeprom@01c14000 { >> >> + compatible = "allwinner,sun4i-a10-sid"; >> >> + reg = <0x01c14000 0x400>; >> > >> > The datasheet says it's 256 bytes wide, while the size here is of 1kB, >> > is it intentional? >> >> My H3 datasheet (v1.1) says its 1 kB wide. > > Is it? in the Security ID section, it is said to be 2kb == 256B wide. Right. I was looking at the memory map. Maybe it's sparsely mapped? I guess we'll know soon. ChenYu >> It'd be nice if Allwinner actually listed the "usable" E-fuse >> offsets and widths, instead of having us dig through the SDK code. > > Yep. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 24 Nov 2015 10:32:02 +0100 From: Maxime Ripard To: Sugar Wu Cc: linux-sunxi , atx@atx.name, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: Re: [linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Message-ID: <20151124093202.GL32142@lukather> References: <20151123124356.GW32142@lukather> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="9RXjJcDGNuBviZqz" In-Reply-To: List-ID: --9RXjJcDGNuBviZqz Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Nov 23, 2015 at 10:51:15PM -0800, Sugar Wu wrote: > On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: > > > > Hi,=20 > > > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:=20 > > > Add a node describing the Security ID memory to the=20 > > > Allwinner H3 .dtsi file.=20 > > >=20 > > > Signed-off-by: Josef Gajdusek >=20 > > > ---=20 > > > arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++=20 > > > 1 file changed, 7 insertions(+)=20 > > >=20 > > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi=20 > > b/arch/arm/boot/dts/sun8i-h3.dtsi=20 > > > index 0faa38a..58de718 100644=20 > > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi=20 > > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi=20 > > > @@ -359,6 +359,13 @@=20 > > > #size-cells =3D <0>;=20 > > > };=20 > > > =20 > > > + sid: eeprom@01c14000 {=20 > > > + compatible =3D "allwinner,sun4i-a10-sid";=20 > > > + reg =3D <0x01c14000 0x400>;=20 > > > > The datasheet says it's 256 bytes wide, while the size here is of 1kB,= =20 > > is it intentional?=20 >=20 > SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space. > H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. Interesting, what is below the 0x200 registers? Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --9RXjJcDGNuBviZqz Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWVC6SAAoJEBx+YmzsjxAgwTAP/R45EtEM0V4qyz9Xbt7PVG4p lgawU8F23DNUZm1piP9JGY/MYxUGTS1E2N3kzAnvfCXUTw9+jns57qQrOIuYTmwQ td8D/Cnvm7xAeFCatj4k/Gs3h5YnbJ0WA8098p+0MxOZI/0VxlMALaNVhPd32piJ +5mBPnV6vc7yjq7tP7GMwpyTgn6jeyLXRyTx8bCrQx99Bd2E/pSK4C51HP4NZGTq S/zD6UI0ddcTIqp3/h7R/stfeAPMfG2U76xIxgIO4Ee7hBpt7n3dKLjoxQEXR9xs d7pXouMv4qt0Dp8FQOKSO2KR/13AptiwIXAiv8pKeyvJx9jehmDBPS3zWcJRKY8F tgMX+yw0qfm0vGUbM71MaZuuQ6p83ubxzjCXOHVeXJzpxMDTjTmjfuz+BRfijU2T d4xA0IGY9DTFCI2tU62QZWghAXV20oNbCZfBOn2meuIw5+TR1iOV25sI46WYci+9 g3qSWeGnRXUovCSEJrPSPWGjKT29z2LoOUXZ6Gy1jHwjF+h9WelL/c0CIq8K6VIA BBzfRa3ny7qC/i8xQRGXIXSbS+DuJB51/9r++AcJQtq9QcFnE/PDN46RvfE6fBU7 e8QI2wcWw5ff+XoZGBaDFWohL5uedLf6en883AnWbhLP7uZ2Rnh2Si6aTEnH7KVI tuziPbgkbQid7tpiEfj5 =bhP/ -----END PGP SIGNATURE----- --9RXjJcDGNuBviZqz-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Mon, 30 Nov 2015 20:58:23 +0100 From: Maxime Ripard To: Josef Gajdusek Cc: linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: Re: [linux-sunxi] Re: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor Message-ID: <20151130195823.GE3664@lukather> References: <20151124084342.GJ32142@lukather> <0edf1031924124377647dfb0f62ec6c8@rainloop.atalax.net> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="KlAEzMkarCnErv5Q" In-Reply-To: <0edf1031924124377647dfb0f62ec6c8@rainloop.atalax.net> List-ID: --KlAEzMkarCnErv5Q Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Nov 25, 2015 at 11:02:34AM +0000, Josef Gajdusek wrote: > >> +struct sun8i_ths_type { > >> + int (*init)(struct platform_device *, struct sun8i_ths_data *); > >> + int (*get_temp)(struct sun8i_ths_data *, int *out); > >> + void (*irq)(struct sun8i_ths_data *); > >> + void (*deinit)(struct sun8i_ths_data *); > >> +}; > >=20 > > AFAIK, you never got back on why it was actually needed, instead of > > directly calling these functions. >=20 > It is preparation for supporting the other SoCs with THS as they have > slightly different register layouts and thus cannot be controlled by the > same code. Do you have support and / or informations on what's going to be needed for these other SoCs yet? Which SoCs are we talking about? > >> + /* The final sample period is calculated as follows: > >> + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) > >> + * > >> + * This results to about 1Hz with these settings. > >> + */ > >> + ret =3D clk_set_rate(data->clk, 4000000); > >=20 > > I don't follow you here. You have a complicated math function, that > > has many input variables, and then, you just set the clock rate to a > > constant? >=20 > How should this be handled then? I guess the sampling rate could > be set in the device tree and then the values calculated, but none > of the other thermal drivers seem to have configurable sample rate. I don't know, I would have expected some actual computation, like a function taking the frequency as a parameter and returning the clock rate. At least that way we now what we're doing and which part might change and which will not. But you do not need to change the sample rate itself. > >> +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *ou= t) > >> +{ > >> + int val =3D readl(data->regs + THS_H3_DATA); > >> + *out =3D sun8i_ths_reg_to_temperature(val, 8253, 217000); > >> + return 0; > >=20 > > Can't you just return the value directly? >=20 > I did that in the v1, clabbe.montjoie suggested to use temp variable to > avoid column wrap. I was talking about the out pointer. Can the value not be returned? > >> + ret =3D devm_request_threaded_irq(&pdev->dev, irq, NULL, > >> + sun8i_ths_irq_thread, IRQF_ONESHOT, > >> + dev_name(&pdev->dev), data); > >=20 > > Why a threaded irq? >=20 > I thought threaded IRQs are preferred? Other thermal drivers > use them too. It's close to pointless in this case. You're not doing much more than what the default handler will do anyway, and you avoid scheduling a thread doing so. And other thermal drivers use a regular interrupt handler too :) > I am also not really sure thermal_zone_device_update() can even be > called in interrupt context. I can't really tell on this one. Judging from a quick look, I can't see anything that could prevent it, and since others are using it, it seems doable. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --KlAEzMkarCnErv5Q Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWXKpfAAoJEBx+YmzsjxAgBeAP/jeiOlcPldKdsFtbtunxaYoA Dv7MhCKdEKi8gG8h1COL8WqpZIS4LmJqBQfdH55naoFXVto6JAIweLJvZJ++kMAI es+05SJEvkx5mu/J02TXeqMaf2P9gvtw1+kktLc/DeNSGG17oK4tF+DCx1BQD/FO r4K62JNTLTzMPIjlH6fvk3cJCvjSa5LzAwzTGDQTlF80fQyl/3nWyrzr+4Vb4sQl lUzuVZelsPoRFI1y0s0xjUUdKYUeAzWpgUT4Wdvh9rxbM/WF98aOFLafiYfU3ulY dpnRbnsKAQ8xTyMcYLUsAgIS3XmBJJuofaK+DoOnwWRgRP5H8V35Rx6DBAuklGnw ahtPHSJqeM/vwF6PGRCnrywP242i+QLiPFLCW5WEpHNwlftYsHtATC0qYhxlehJ4 iJkJoOu0X+cOVSnoIz3tpmD2q1dMR9cD2yGFm8Yg4q10EW8ox2IlV+xORs7nD37A 3vbOzz3nYGjbkGD4vwHIs8MNZF8P+zJIrGFnPpZVwX2VjUnaAQ8lhxI3vdhm195D q7S4LRD1VSqzMxucfGQX2AJ7EyZwgW9gmQygPkPQ0jE4PNTTMTGw/kENH+ixLjG5 gNUGxmCybl0NOmvwE5PhZGgh6aX5g1A70QiWjzyhOM5LFAXWP9Wr2Znojd8Fixju wSvwcXRh5LPLjmP4XYpY =4m++ -----END PGP SIGNATURE----- --KlAEzMkarCnErv5Q-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Josef Gajdusek To: linux-sunxi@googlegroups.com Cc: Josef Gajdusek , linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, maxime.ripard@free-electrons.com, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: [PATCH v2 0/5] sunxi: THS support Date: Mon, 23 Nov 2015 09:02:47 +0100 Message-Id: List-ID: Hello everyone, this is v2 of my THS patchset Changelog: * Some stylistic changes * devm_reset_control_get_optional -> devm_reset_control_get * Added the clk-h3-ths clock driver - Note: A23/A33/A83T do not have a separate clock, H3 seems to be the first (and only?) SoC with it - Because of this, I moved the clock init code to the H3-specific init function. * Use the nvmem cell abstraction instead of accessing the configuration memory directly * Use the IRQ line (and fixed incorrect interrupt number in the DTS) * Renamed to sun8i_ths Ad the "magical constants": what I meant is that altough the datasheet explains what they are, it does not explain how to pick their values. "ADC" and "Sensor" "acquire time" are also not exactly the most helpful descriptions. Anyway, I changed the values such as the final sampling rate is about 1Hz. Josef Gajdusek (5): ARM: dts: sun8i: Add SID node clk: sunxi: Add driver for the H3 THS clock thermal: Add a driver for the Allwinner THS sensor dt-bindings: document sun8i_ths ARM: dts: sun8i: Add THS node to the H3 .dtsi Documentation/devicetree/bindings/clock/sunxi.txt | 1 + .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++ arch/arm/boot/dts/sun8i-h3.dtsi | 40 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-h3-ths.c | 98 ++++++ drivers/thermal/Kconfig | 7 + drivers/thermal/Makefile | 1 + drivers/thermal/sun8i_ths.c | 365 +++++++++++++++++++++ 8 files changed, 544 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt create mode 100644 drivers/clk/sunxi/clk-h3-ths.c create mode 100644 drivers/thermal/sun8i_ths.c -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Message-ID: <1448274489.27496.1.camel@plaes.org> Subject: Re: [linux-sunxi] [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock From: Priit Laes To: atx@atx.name, linux-sunxi@googlegroups.com Cc: linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, maxime.ripard@free-electrons.com, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Date: Mon, 23 Nov 2015 12:28:09 +0200 In-Reply-To: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> References: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 List-ID: On Mon, 2015-11-23 at 09:02 +0100, Josef Gajdusek wrote: > This patch adds a driver for the THS clock which is present on the > Allwinner H3. > > Signed-off-by: Josef Gajdusek > --- >  Documentation/devicetree/bindings/clock/sunxi.txt |  1 + >  drivers/clk/sunxi/Makefile                        |  1 + >  drivers/clk/sunxi/clk-h3-ths.c                    | 98 > +++++++++++++++++++++++ >  3 files changed, 100 insertions(+) >  create mode 100644 drivers/clk/sunxi/clk-h3-ths.c > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt > b/Documentation/devicetree/bindings/clock/sunxi.txt > index 23e7bce..6d63b35 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -73,6 +73,7 @@ Required properties: >   "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 >   "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets > on A80 >   "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + > resets on A80 > + "allwinner,sun8i-h3-ths-clk" - for THS on H3 >   >  Required properties for all clocks: >  - reg : shall be the control register address for the clock. > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index f520af6..1bf8e1c 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -8,6 +8,7 @@ obj-y += clk-a10-hosc.o >  obj-y += clk-a10-mod1.o >  obj-y += clk-a10-pll2.o >  obj-y += clk-a20-gmac.o > +obj-y += clk-h3-ths.o >  obj-y += clk-mod0.o >  obj-y += clk-simple-gates.o >  obj-y += clk-sun8i-bus-gates.o > diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk- > h3-ths.c > new file mode 100644 > index 0000000..663afc0 > --- /dev/null > +++ b/drivers/clk/sunxi/clk-h3-ths.c > @@ -0,0 +1,98 @@ > +/* > + * Sunxi THS clock driver This should be "Allwinner H3 THS clock driver" > + * > + * Copyright (C) 2015 Josef Gajdusek > + * > + * This software is licensed under the terms of the GNU General > Public > + * License version 2, as published by the Free Software Foundation, > and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > + > +#define SUN8I_H3_THS_CLK_ENABLE 31 > +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0 > +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2 > + > +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock); > + > +static const struct clk_div_table sun8i_h3_ths_clk_table[] > __initconst = { > + { .val = 0, .div = 1 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 6 }, > + { } /* sentinel */ > +}; > + > +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) > +{ > + struct clk *clk; > + struct clk_gate *gate; > + struct clk_divider *div; > + const char *parent; > + const char *clk_name = node->name; > + void __iomem *reg; > + int err; > + > + reg = of_io_request_and_map(node, 0, > of_node_full_name(node)); > + > + if (IS_ERR(reg)) > + return; > + > + gate = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!gate) > + goto err_unmap; > + > + div = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!div) > + goto err_gate_free; > + > + of_property_read_string(node, "clock-output-names", > &clk_name); > + parent = of_clk_get_parent_name(node, 0); > + > + gate->reg = reg; > + gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE; > + gate->lock = &sun8i_h3_ths_clk_lock; > + > + div->reg = reg; > + div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT; > + div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH; > + div->table = sun8i_h3_ths_clk_table; > + div->lock = &sun8i_h3_ths_clk_lock; > + > + clk = clk_register_composite(NULL, clk_name, &parent, 1, > +      NULL, NULL, > +      &div->hw, &clk_divider_ops, > +      &gate->hw, &clk_gate_ops, > +      CLK_SET_RATE_PARENT); > + > + if (IS_ERR(clk)) > + goto err_div_free; > + > + err = of_clk_add_provider(node, of_clk_src_simple_get, clk); > + if (err) > + goto err_unregister_clk; > + > + return; > + > +err_unregister_clk: > + clk_unregister(clk); > +err_gate_free: > + kfree(gate); > +err_div_free: > + kfree(div); > +err_unmap: > + iounmap(reg); > +} > + > +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk", > +        sun8i_h3_ths_clk_setup); > -- > 2.4.10 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 In-Reply-To: <20151123124356.GW32142@lukather> References: <20151123124356.GW32142@lukather> From: Chen-Yu Tsai Date: Tue, 24 Nov 2015 11:13:13 +0800 Message-ID: Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node To: Maxime Ripard Cc: Josef Gajdusek , linux-sunxi , linux-clk , linux-pm@vger.kernel.org, linux-kernel , linux-arm-kernel , devicetree , gpatchesrdh@mveas.com, Mike Turquette , Hans De Goede , Stephen Boyd , Michael Turquette , Emilio Lopez , Russell King - ARM Linux , Eduardo Valentin , Zhang Rui , Chen-Yu Tsai , Kumar Gala , Ian Campbell , Mark Rutland , Pawel Moll , Rob Herring Content-Type: text/plain; charset=UTF-8 List-ID: Hi, On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard wrote: > Hi, > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: >> Add a node describing the Security ID memory to the >> Allwinner H3 .dtsi file. >> >> Signed-off-by: Josef Gajdusek >> --- >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi >> index 0faa38a..58de718 100644 >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >> @@ -359,6 +359,13 @@ >> #size-cells = <0>; >> }; >> >> + sid: eeprom@01c14000 { >> + compatible = "allwinner,sun4i-a10-sid"; >> + reg = <0x01c14000 0x400>; > > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > is it intentional? My H3 datasheet (v1.1) says its 1 kB wide. It'd be nice if Allwinner actually listed the "usable" E-fuse offsets and widths, instead of having us dig through the SDK code. Regards ChenYu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Josef Gajdusek To: linux-sunxi@googlegroups.com Cc: Josef Gajdusek , linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, maxime.ripard@free-electrons.com, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor Date: Mon, 23 Nov 2015 09:02:50 +0100 Message-Id: In-Reply-To: References: In-Reply-To: References: List-ID: This patch adds support for the Sunxi thermal sensor on the Allwinner H3. Should be easily extendable for the A33/A83T/... as they have similar but not completely identical sensors. Signed-off-by: Josef Gajdusek --- drivers/thermal/Kconfig | 7 + drivers/thermal/Makefile | 1 + drivers/thermal/sun8i_ths.c | 365 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 373 insertions(+) create mode 100644 drivers/thermal/sun8i_ths.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index c463c89..2b41147 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config SUN8I_THS + tristate "sun8i THS driver" + depends on MACH_SUN8I + depends on OF + help + Enable this to support thermal reporting on some newer Allwinner SoCs. + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index cfae6a6..227e1a1 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_SUN8I_THS) += sun8i_ths.o diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c new file mode 100644 index 0000000..2c976ac --- /dev/null +++ b/drivers/thermal/sun8i_ths.c @@ -0,0 +1,365 @@ +/* + * Sunxi THS driver + * + * Copyright (C) 2015 Josef Gajdusek + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define THS_H3_CTRL0 0x00 +#define THS_H3_CTRL1 0x04 +#define THS_H3_CDAT 0x14 +#define THS_H3_CTRL2 0x40 +#define THS_H3_INT_CTRL 0x44 +#define THS_H3_STAT 0x48 +#define THS_H3_ALARM_CTRL 0x50 +#define THS_H3_SHUTDOWN_CTRL 0x60 +#define THS_H3_FILTER 0x70 +#define THS_H3_CDATA 0x74 +#define THS_H3_DATA 0x80 + +#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS 0 +#define THS_H3_CTRL0_SENSOR_ACQ0(x) \ + ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS) +#define THS_H3_CTRL1_ADC_CALI_EN_OFFS 17 +#define THS_H3_CTRL1_ADC_CALI_EN \ + BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS) +#define THS_H3_CTRL1_OP_BIAS_OFFS 20 +#define THS_H3_CTRL1_OP_BIAS(x) \ + ((x) << THS_H3_CTRL1_OP_BIAS_OFFS) +#define THS_H3_CTRL2_SENSE_EN_OFFS 0 +#define THS_H3_CTRL2_SENSE_EN \ + BIT(THS_H3_CTRL2_SENSE_EN_OFFS) +#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS 16 +#define THS_H3_CTRL2_SENSOR_ACQ1(x) \ + ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS) + +#define THS_H3_INT_CTRL_ALARM_INT_EN_OFFS 0 +#define THS_H3_INT_CTRL_ALARM_INT_EN \ + BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS) +#define THS_H3_INT_CTRL_SHUT_INT_EN_OFFS 4 +#define THS_H3_INT_CTRL_SHUT_INT_EN \ + BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS) +#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS 8 +#define THS_H3_INT_CTRL_DATA_IRQ_EN \ + BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS) +#define THS_H3_INT_CTRL_THERMAL_PER_OFFS 12 +#define THS_H3_INT_CTRL_THERMAL_PER(x) \ + ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS) + +#define THS_H3_STAT_ALARM_INT_STS_OFFS 0 +#define THS_H3_STAT_ALARM_INT_STS \ + BIT(THS_H3_STAT_ALARM_INT_STS_OFFS) +#define THS_H3_STAT_SHUT_INT_STS_OFFS 4 +#define THS_H3_STAT_SHUT_INT_STS \ + BIT(THS_H3_STAT_SHUT_INT_STS_OFFS) +#define THS_H3_STAT_DATA_IRQ_STS_OFFS 8 +#define THS_H3_STAT_DATA_IRQ_STS \ + BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS) +#define THS_H3_STAT_ALARM_OFF_STS_OFFS 12 +#define THS_H3_STAT_ALARM_OFF_STS \ + BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS) + +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS 0 +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST(x) \ + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS) +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS 16 +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT(x) \ + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS) + +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS 16 +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT(x) \ + ((x) << THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS) + +#define THS_H3_FILTER_TYPE_OFFS 0 +#define THS_H3_FILTER_TYPE(x) \ + ((x) << THS_H3_FILTER_TYPE_OFFS) +#define THS_H3_FILTER_EN_OFFS 2 +#define THS_H3_FILTER_EN \ + BIT(THS_H3_FILTER_EN_OFFS) + +#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0xff +#define THS_H3_INT_CTRL_THERMAL_PER_VALUE 0x79 +#define THS_H3_FILTER_TYPE_VALUE 0x2 +#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f + +struct sun8i_ths_data { + struct sun8i_ths_type *type; + struct reset_control *reset; + struct clk *clk; + struct clk *busclk; + void __iomem *regs; + struct nvmem_cell *calcell; + struct platform_device *pdev; + struct thermal_zone_device *tzd; +}; + +struct sun8i_ths_type { + int (*init)(struct platform_device *, struct sun8i_ths_data *); + int (*get_temp)(struct sun8i_ths_data *, int *out); + void (*irq)(struct sun8i_ths_data *); + void (*deinit)(struct sun8i_ths_data *); +}; + +/* Formula and parameters from the Allwinner 3.4 kernel */ +static int sun8i_ths_reg_to_temperature(s32 reg, int divisor, int constant) +{ + return constant - (reg * 1000000) / divisor; +} + +static int sun8i_ths_get_temp(void *_data, int *out) +{ + struct sun8i_ths_data *data = _data; + + return data->type->get_temp(data, out); +} + +static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data) +{ + struct sun8i_ths_data *data = _data; + + data->type->irq(data); + thermal_zone_device_update(data->tzd); + + return IRQ_HANDLED; +} + +static int sun8i_ths_h3_init(struct platform_device *pdev, + struct sun8i_ths_data *data) +{ + int ret; + size_t callen; + s32 *caldata; + + data->busclk = devm_clk_get(&pdev->dev, "ahb"); + if (IS_ERR(data->busclk)) { + ret = PTR_ERR(data->busclk); + dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret); + return ret; + } + + data->clk = devm_clk_get(&pdev->dev, "ths"); + if (IS_ERR(data->clk)) { + ret = PTR_ERR(data->clk); + dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret); + return ret; + } + + data->reset = devm_reset_control_get(&pdev->dev, "ahb"); + if (IS_ERR(data->reset)) { + ret = PTR_ERR(data->reset); + dev_err(&pdev->dev, "failed to get reset: %d\n", ret); + return ret; + } + + if (data->calcell) { + caldata = nvmem_cell_read(data->calcell, &callen); + if (IS_ERR(caldata)) + return PTR_ERR(caldata); + writel(be32_to_cpu(*caldata), data->regs + THS_H3_CDATA); + kfree(caldata); + } + + ret = clk_prepare_enable(data->busclk); + if (ret) { + dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(data->clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret); + goto err_disable_bus; + } + + ret = reset_control_deassert(data->reset); + if (ret) { + dev_err(&pdev->dev, "reset deassert failed: %d\n", ret); + goto err_disable_ths; + } + + /* The final sample period is calculated as follows: + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) + * + * This results to about 1Hz with these settings. + */ + ret = clk_set_rate(data->clk, 4000000); + if (ret) + goto err_disable_ths; + writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE), + data->regs + THS_H3_CTRL0); + writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) | + THS_H3_INT_CTRL_DATA_IRQ_EN, + data->regs + THS_H3_INT_CTRL); + writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE), + data->regs + THS_H3_FILTER); + writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) | + THS_H3_CTRL2_SENSE_EN, + data->regs + THS_H3_CTRL2); + return 0; + +err_disable_ths: + clk_disable_unprepare(data->clk); +err_disable_bus: + clk_disable_unprepare(data->busclk); + + return ret; +} + +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *out) +{ + int val = readl(data->regs + THS_H3_DATA); + *out = sun8i_ths_reg_to_temperature(val, 8253, 217000); + return 0; +} + +static void sun8i_ths_h3_irq(struct sun8i_ths_data *data) +{ + writel(THS_H3_STAT_DATA_IRQ_STS | + THS_H3_STAT_ALARM_INT_STS | + THS_H3_STAT_ALARM_OFF_STS | + THS_H3_STAT_SHUT_INT_STS, + data->regs + THS_H3_STAT); +} + +static void sun8i_ths_h3_deinit(struct sun8i_ths_data *data) +{ + reset_control_assert(data->reset); + clk_disable_unprepare(data->clk); + clk_disable_unprepare(data->busclk); +} + +static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = { + .get_temp = sun8i_ths_get_temp, +}; + +static const struct sun8i_ths_type sun8i_ths_device_h3 = { + .init = sun8i_ths_h3_init, + .get_temp = sun8i_ths_h3_get_temp, + .irq = sun8i_ths_h3_irq, + .deinit = sun8i_ths_h3_deinit, +}; + +static const struct of_device_id sun8i_ths_id_table[] = { + { + .compatible = "allwinner,sun8i-h3-ths", + .data = &sun8i_ths_device_h3, + }, + { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, sun8i_ths_id_table); + +static int sun8i_ths_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + struct sun8i_ths_data *data; + struct resource *res; + int ret; + int irq; + + match = of_match_node(sun8i_ths_id_table, np); + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->type = (struct sun8i_ths_type *)match->data; + data->pdev = pdev; + + data->calcell = devm_nvmem_cell_get(&pdev->dev, "calibration"); + if (IS_ERR(data->calcell)) { + if (PTR_ERR(data->calcell) == -EPROBE_DEFER) + return PTR_ERR(data->calcell); + data->calcell = NULL; /* No calibration register */ + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->regs)) { + ret = PTR_ERR(data->regs); + dev_err(&pdev->dev, + "failed to ioremap THS registers: %d\n", ret); + return ret; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); + return irq; + } + + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, + sun8i_ths_irq_thread, IRQF_ONESHOT, + dev_name(&pdev->dev), data); + if (ret) + return ret; + + ret = data->type->init(pdev, data); + if (ret) + return ret; + + data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, + &sun8i_ths_thermal_ops); + if (IS_ERR(data->tzd)) { + ret = PTR_ERR(data->tzd); + dev_err(&pdev->dev, "failed to register thermal zone: %d\n", + ret); + goto err_deinit; + } + + platform_set_drvdata(pdev, data); + return 0; + +err_deinit: + data->type->deinit(data); + return ret; +} + +static int sun8i_ths_remove(struct platform_device *pdev) +{ + struct sun8i_ths_data *data = platform_get_drvdata(pdev); + + thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); + data->type->deinit(data); + return 0; +} + +static struct platform_driver sun8i_ths_driver = { + .probe = sun8i_ths_probe, + .remove = sun8i_ths_remove, + .driver = { + .name = "sun8i_ths", + .of_match_table = sun8i_ths_id_table, + }, +}; + +module_platform_driver(sun8i_ths_driver); + +MODULE_AUTHOR("Josef Gajdusek "); +MODULE_DESCRIPTION("Sunxi THS driver"); +MODULE_LICENSE("GPL v2"); -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Josef Gajdusek To: linux-sunxi@googlegroups.com Cc: Josef Gajdusek , linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, maxime.ripard@free-electrons.com, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Mon, 23 Nov 2015 09:02:48 +0100 Message-Id: In-Reply-To: References: In-Reply-To: References: List-ID: Add a node describing the Security ID memory to the Allwinner H3 .dtsi file. Signed-off-by: Josef Gajdusek --- arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 0faa38a..58de718 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -359,6 +359,13 @@ #size-cells = <0>; }; + sid: eeprom@01c14000 { + compatible = "allwinner,sun4i-a10-sid"; + reg = <0x01c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + usbphy: phy@01c19400 { compatible = "allwinner,sun8i-h3-usb-phy"; reg = <0x01c19400 0x2c>, -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Josef Gajdusek To: linux-sunxi@googlegroups.com Cc: Josef Gajdusek , linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, maxime.ripard@free-electrons.com, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock Date: Mon, 23 Nov 2015 09:02:49 +0100 Message-Id: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> In-Reply-To: References: In-Reply-To: References: List-ID: This patch adds a driver for the THS clock which is present on the Allwinner H3. Signed-off-by: Josef Gajdusek --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-h3-ths.c | 98 +++++++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/clk/sunxi/clk-h3-ths.c diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 23e7bce..6d63b35 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -73,6 +73,7 @@ Required properties: "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 + "allwinner,sun8i-h3-ths-clk" - for THS on H3 Required properties for all clocks: - reg : shall be the control register address for the clock. diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index f520af6..1bf8e1c 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -8,6 +8,7 @@ obj-y += clk-a10-hosc.o obj-y += clk-a10-mod1.o obj-y += clk-a10-pll2.o obj-y += clk-a20-gmac.o +obj-y += clk-h3-ths.o obj-y += clk-mod0.o obj-y += clk-simple-gates.o obj-y += clk-sun8i-bus-gates.o diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk-h3-ths.c new file mode 100644 index 0000000..663afc0 --- /dev/null +++ b/drivers/clk/sunxi/clk-h3-ths.c @@ -0,0 +1,98 @@ +/* + * Sunxi THS clock driver + * + * Copyright (C) 2015 Josef Gajdusek + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#define SUN8I_H3_THS_CLK_ENABLE 31 +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0 +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2 + +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock); + +static const struct clk_div_table sun8i_h3_ths_clk_table[] __initconst = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 6 }, + { } /* sentinel */ +}; + +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) +{ + struct clk *clk; + struct clk_gate *gate; + struct clk_divider *div; + const char *parent; + const char *clk_name = node->name; + void __iomem *reg; + int err; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + + if (IS_ERR(reg)) + return; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto err_unmap; + + div = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!div) + goto err_gate_free; + + of_property_read_string(node, "clock-output-names", &clk_name); + parent = of_clk_get_parent_name(node, 0); + + gate->reg = reg; + gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE; + gate->lock = &sun8i_h3_ths_clk_lock; + + div->reg = reg; + div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT; + div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH; + div->table = sun8i_h3_ths_clk_table; + div->lock = &sun8i_h3_ths_clk_lock; + + clk = clk_register_composite(NULL, clk_name, &parent, 1, + NULL, NULL, + &div->hw, &clk_divider_ops, + &gate->hw, &clk_gate_ops, + CLK_SET_RATE_PARENT); + + if (IS_ERR(clk)) + goto err_div_free; + + err = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (err) + goto err_unregister_clk; + + return; + +err_unregister_clk: + clk_unregister(clk); +err_gate_free: + kfree(gate); +err_div_free: + kfree(div); +err_unmap: + iounmap(reg); +} + +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk", + sun8i_h3_ths_clk_setup); -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 24 Nov 2015 07:38:09 +0100 From: Maxime Ripard To: Chen-Yu Tsai Cc: Josef Gajdusek , linux-sunxi , linux-clk , linux-pm@vger.kernel.org, linux-kernel , linux-arm-kernel , devicetree , gpatchesrdh@mveas.com, Mike Turquette , Hans De Goede , Stephen Boyd , Michael Turquette , Emilio Lopez , Russell King - ARM Linux , Eduardo Valentin , Zhang Rui , Kumar Gala , Ian Campbell , Mark Rutland , Pawel Moll , Rob Herring Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Message-ID: <20151124063808.GB32142@lukather> References: <20151123124356.GW32142@lukather> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Cjvo8w+V8lMs5Jsv" In-Reply-To: List-ID: --Cjvo8w+V8lMs5Jsv Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Nov 24, 2015 at 11:13:13AM +0800, Chen-Yu Tsai wrote: > Hi, >=20 > On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard > wrote: > > Hi, > > > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > >> Add a node describing the Security ID memory to the > >> Allwinner H3 .dtsi file. > >> > >> Signed-off-by: Josef Gajdusek > >> --- > >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > >> 1 file changed, 7 insertions(+) > >> > >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i= -h3.dtsi > >> index 0faa38a..58de718 100644 > >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi > >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > >> @@ -359,6 +359,13 @@ > >> #size-cells =3D <0>; > >> }; > >> > >> + sid: eeprom@01c14000 { > >> + compatible =3D "allwinner,sun4i-a10-sid"; > >> + reg =3D <0x01c14000 0x400>; > > > > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > > is it intentional? >=20 > My H3 datasheet (v1.1) says its 1 kB wide. Is it? in the Security ID section, it is said to be 2kb =3D=3D 256B wide. > It'd be nice if Allwinner actually listed the "usable" E-fuse > offsets and widths, instead of having us dig through the SDK code. Yep. Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --Cjvo8w+V8lMs5Jsv Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWVAXQAAoJEBx+YmzsjxAgPQYP/iP6PvN/UMQmKwO0HR7KEgZw Pwyg9fx0eoZkBqyS1chxiQ1ptFLKlEgHlorthCa5F67e+b1968vMrLYnZrALTDCO zd+9ktnNAgU4QaHo6qbE0ThDkHd5qFd3bshnBijLnD2vEhWOjX6Ec1Y/XJoZDV1Y FuezTZeyM2stHSoL+dLHw3XU2T6Zef2V5u0iqgStqzsdhwM5bo5+vi5srVKPzvnX WZyRsJHhQ9v+1gcOLjx5RdVPe4egh/5WEGoCGdLb7c7dJF2CmQICdhyOA+r/Bhe5 Oi6F1N65bnEFss36dqDM+Ql6Z7xf39vI5aJ0vqtabUSPFLlVMwWf31Ezao1fQQNT hHarPjEqMRCCYo9mpCrZnZnRc7eVI3WNwo4C6t0WYPb6Gyfp6X2rCThBp5QTGH54 fQJTm7rJ6hq94miYxpO6p6ldXIQOxK/BgBs5KeAuH8w6cnLj7t5eUCD1xoWeQ5li 7Kz5AfYgmyjR9nK1TT1COkQd37JDLKxq39dqrDWdJ4PLUrB6E78RuYvPlnD0Ebms bzNW5ZQVXcBCCe7eRvmBHi327LhMZeXc81/qyzXwiAPu2s7bZA9N9oHsSh3op5RF TJNca13GyCuKCP475gVEA8HhRZVLUZSM13TEuE5MH4rHxk2GI3NRyZEnPgcAsV0O NYmbhaYx2Ac8spijiTEK =hDTM -----END PGP SIGNATURE----- --Cjvo8w+V8lMs5Jsv-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: From: Shuge Subject: Re: [linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node To: Maxime Ripard References: <20151123124356.GW32142@lukather> <20151124093202.GL32142@lukather> Cc: linux-sunxi , atx@atx.name, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Message-ID: <56550D70.6060109@gmail.com> Date: Wed, 25 Nov 2015 09:22:56 +0800 MIME-Version: 1.0 In-Reply-To: <20151124093202.GL32142@lukather> Content-Type: text/plain; charset=windows-1252 List-ID: On Monday, November 23, 2015 at 17:32 UTC+8, Maxime Ripard wrote: > On Mon, Nov 23, 2015 at 10:51:15PM -0800, Sugar Wu wrote: >> On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: >>> >>> Hi, >>> >>> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: >>>> Add a node describing the Security ID memory to the >>>> Allwinner H3 .dtsi file. >>>> >>>> Signed-off-by: Josef Gajdusek > >>>> --- >>>> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ >>>> 1 file changed, 7 insertions(+) >>>> >>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi >>> b/arch/arm/boot/dts/sun8i-h3.dtsi >>>> index 0faa38a..58de718 100644 >>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi >>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >>>> @@ -359,6 +359,13 @@ >>>> #size-cells = <0>; >>>> }; >>>> >>>> + sid: eeprom@01c14000 { >>>> + compatible = "allwinner,sun4i-a10-sid"; >>>> + reg = <0x01c14000 0x400>; >>> >>> The datasheet says it's 256 bytes wide, while the size here is of 1kB, >>> is it intentional? >> >> SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space. >> H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. > > Interesting, what is below the 0x200 registers? > Some control register about SID. offset: 0x40 SID Program/Read Control Register offset: 0x50 SID Program Key Value Register offset: 0x60 SID Read Key Value Register offset: 0x70 \ offset: 0x80 SJTAG Attribute 0 Register offset: 0x84 SJTAG Attribute 1 Register offset: 0x88 SJTAG Select Register offset: 0x90 SID Program Ctrol register for burned timing > > Thanks! > Maxime > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Mime-Version: 1.0 Date: Wed, 25 Nov 2015 11:02:34 +0000 Content-Type: text/plain; charset="utf-8" Message-ID: <0edf1031924124377647dfb0f62ec6c8@rainloop.atalax.net> From: "Josef Gajdusek" Subject: Re: [linux-sunxi] Re: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor To: maxime.ripard@free-electrons.com Cc: linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org In-Reply-To: <20151124084342.GJ32142@lukather> References: <20151124084342.GJ32142@lukather> List-ID: November 24 2015 9:43 AM, "Maxime Ripard" wrote:=0A=0A> On Mon, Nov 23, 2015 at 09:02:50AM +0100, Josef Gajduse= k wrote:=0A> =0A>> This patch adds support for the Sunxi thermal sensor o= n the Allwinner H3.=0A> =0A> You can drop the sunxi here.=0A> =0A>> Shoul= d be easily extendable for the A33/A83T/... as they have similar but=0A>>= not completely identical sensors.=0A>> =0A>> Signed-off-by: Josef Gajdus= ek =0A>> ---=0A>> drivers/thermal/Kconfig | 7 +=0A>> driver= s/thermal/Makefile | 1 +=0A>> drivers/thermal/sun8i_ths.c | 365 +++++++++= +++++++++++++++++++++++++++++++++++=0A>> 3 files changed, 373 insertions(= +)=0A>> create mode 100644 drivers/thermal/sun8i_ths.c=0A>> =0A>> diff --= git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig=0A>> index c463c8= 9..2b41147 100644=0A>> --- a/drivers/thermal/Kconfig=0A>> +++ b/drivers/t= hermal/Kconfig=0A>> @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL=0A>> Th= ermal reporting device will provide temperature reading,=0A>> programmabl= e trip points and other information.=0A>> =0A>> +config SUN8I_THS=0A>> + = tristate "sun8i THS driver"=0A>> + depends on MACH_SUN8I=0A>> + depends o= n OF=0A>> + help=0A>> + Enable this to support thermal reporting on some = newer Allwinner SoCs.=0A>> +=0A>> menu "Texas Instruments thermal drivers= "=0A>> depends on ARCH_HAS_BANDGAP || COMPILE_TEST=0A>> source "drivers/t= hermal/ti-soc-thermal/Kconfig"=0A>> diff --git a/drivers/thermal/Makefile= b/drivers/thermal/Makefile=0A>> index cfae6a6..227e1a1 100644=0A>> --- a= /drivers/thermal/Makefile=0A>> +++ b/drivers/thermal/Makefile=0A>> @@ -48= ,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) +=3D intel_pch_thermal.o=0A>>= obj-$(CONFIG_ST_THERMAL) +=3D st/=0A>> obj-$(CONFIG_TEGRA_SOCTHERM) +=3D= tegra_soctherm.o=0A>> obj-$(CONFIG_HISI_THERMAL) +=3D hisi_thermal.o=0A>= > +obj-$(CONFIG_SUN8I_THS) +=3D sun8i_ths.o=0A>> diff --git a/drivers/the= rmal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c=0A>> new file mode 100644= =0A>> index 0000000..2c976ac=0A>> --- /dev/null=0A>> +++ b/drivers/therma= l/sun8i_ths.c=0A>> @@ -0,0 +1,365 @@=0A>> +/*=0A>> + * Sunxi THS driver= =0A> =0A> sun8i Thermal Sensor Driver=0A> =0A>> + * Copyright (C) 2015 Jo= sef Gajdusek=0A>> + *=0A>> + * This software is licensed under the terms = of the GNU General Public=0A>> + * License version 2, as published by the= Free Software Foundation, and=0A>> + * may be copied, distributed, and m= odified under those terms.=0A>> + *=0A>> + * This program is distributed = in the hope that it will be useful,=0A>> + * but WITHOUT ANY WARRANTY; wi= thout even the implied warranty of=0A>> + * MERCHANTABILITY or FITNESS FO= R A PARTICULAR PURPOSE. See the=0A>> + * GNU General Public License for m= ore details.=0A>> + *=0A>> + */=0A>> +=0A>> +#include =0A>> = +#include =0A> =0A> Are you using this header?=0A> =0A>> += #include =0A>> +#include =0A>> +#include <= linux/irq.h>=0A> =0A> You probably don't need this one too.=0A> =0A>> +#i= nclude =0A>> +#include =0A>> +#in= clude =0A>> +#include =0A>> += #include =0A>> +#include =0A>> +#include <= linux/slab.h>=0A>> +#include =0A>> +=0A>> +#define THS_H= 3_CTRL0 0x00=0A>> +#define THS_H3_CTRL1 0x04=0A>> +#define THS_H3_CDAT 0x= 14=0A>> +#define THS_H3_CTRL2 0x40=0A>> +#define THS_H3_INT_CTRL 0x44=0A>= > +#define THS_H3_STAT 0x48=0A>> +#define THS_H3_ALARM_CTRL 0x50=0A>> +#d= efine THS_H3_SHUTDOWN_CTRL 0x60=0A>> +#define THS_H3_FILTER 0x70=0A>> +#d= efine THS_H3_CDATA 0x74=0A>> +#define THS_H3_DATA 0x80=0A>> +=0A>> +#defi= ne THS_H3_CTRL0_SENSOR_ACQ0_OFFS 0=0A>> +#define THS_H3_CTRL0_SENSOR_ACQ0= (x) \=0A>> + ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS)=0A>> +#define THS_H3_= CTRL1_ADC_CALI_EN_OFFS 17=0A>> +#define THS_H3_CTRL1_ADC_CALI_EN \=0A>> += BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS)=0A>> +#define THS_H3_CTRL1_OP_BIAS_OF= FS 20=0A>> +#define THS_H3_CTRL1_OP_BIAS(x) \=0A>> + ((x) << THS_H3_CTRL1= _OP_BIAS_OFFS)=0A>> +#define THS_H3_CTRL2_SENSE_EN_OFFS 0=0A>> +#define T= HS_H3_CTRL2_SENSE_EN \=0A>> + BIT(THS_H3_CTRL2_SENSE_EN_OFFS)=0A>> +#defi= ne THS_H3_CTRL2_SENSOR_ACQ1_OFFS 16=0A>> +#define THS_H3_CTRL2_SENSOR_ACQ= 1(x) \=0A>> + ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS)=0A>> +=0A>> +#define= THS_H3_INT_CTRL_ALARM_INT_EN_OFFS 0=0A>> +#define THS_H3_INT_CTRL_ALARM_= INT_EN \=0A>> + BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS)=0A>> +#define THS_= H3_INT_CTRL_SHUT_INT_EN_OFFS 4=0A>> +#define THS_H3_INT_CTRL_SHUT_INT_EN = \=0A>> + BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS)=0A>> +#define THS_H3_INT_C= TRL_DATA_IRQ_EN_OFFS 8=0A>> +#define THS_H3_INT_CTRL_DATA_IRQ_EN \=0A>> += BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS)=0A>> +#define THS_H3_INT_CTRL_THER= MAL_PER_OFFS 12=0A>> +#define THS_H3_INT_CTRL_THERMAL_PER(x) \=0A>> + ((x= ) << THS_H3_INT_CTRL_THERMAL_PER_OFFS)=0A>> +=0A>> +#define THS_H3_STAT_A= LARM_INT_STS_OFFS 0=0A>> +#define THS_H3_STAT_ALARM_INT_STS \=0A>> + BIT(= THS_H3_STAT_ALARM_INT_STS_OFFS)=0A>> +#define THS_H3_STAT_SHUT_INT_STS_OF= FS 4=0A>> +#define THS_H3_STAT_SHUT_INT_STS \=0A>> + BIT(THS_H3_STAT_SHUT= _INT_STS_OFFS)=0A>> +#define THS_H3_STAT_DATA_IRQ_STS_OFFS 8=0A>> +#defin= e THS_H3_STAT_DATA_IRQ_STS \=0A>> + BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS)=0A= >> +#define THS_H3_STAT_ALARM_OFF_STS_OFFS 12=0A>> +#define THS_H3_STAT_A= LARM_OFF_STS \=0A>> + BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS)=0A>> +=0A>> +#d= efine THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS 0=0A>> +#define THS_H3_ALARM_C= TRL_ALARM0_T_HYST(x) \=0A>> + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFF= S)=0A>> +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS 16=0A>> +#define THS= _H3_ALARM_CTRL_ALARM0_T_HOT(x) \=0A>> + ((x) << THS_H3_ALARM_CTRL_ALARM0_= T_HOT_OFFS)=0A>> +=0A>> +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS 16= =0A>> +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT(x) \=0A>> + ((x) << THS_H= 3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS)=0A>> +=0A>> +#define THS_H3_FILTER_TYPE= _OFFS 0=0A>> +#define THS_H3_FILTER_TYPE(x) \=0A>> + ((x) << THS_H3_FILTE= R_TYPE_OFFS)=0A>> +#define THS_H3_FILTER_EN_OFFS 2=0A>> +#define THS_H3_F= ILTER_EN \=0A>> + BIT(THS_H3_FILTER_EN_OFFS)=0A> =0A> Are you using these= offsets anywhere?=0A>> +=0A>> +#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0x= ff=0A>> +#define THS_H3_INT_CTRL_THERMAL_PER_VALUE 0x79=0A>> +#define THS= _H3_FILTER_TYPE_VALUE 0x2=0A>> +#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x= 3f=0A>> +=0A>> +struct sun8i_ths_data {=0A>> + struct sun8i_ths_type *typ= e;=0A>> + struct reset_control *reset;=0A>> + struct clk *clk;=0A>> + str= uct clk *busclk;=0A>> + void __iomem *regs;=0A>> + struct nvmem_cell *cal= cell;=0A>> + struct platform_device *pdev;=0A>> + struct thermal_zone_dev= ice *tzd;=0A>> +};=0A>> +=0A>> +struct sun8i_ths_type {=0A>> + int (*init= )(struct platform_device *, struct sun8i_ths_data *);=0A>> + int (*get_te= mp)(struct sun8i_ths_data *, int *out);=0A>> + void (*irq)(struct sun8i_t= hs_data *);=0A>> + void (*deinit)(struct sun8i_ths_data *);=0A>> +};=0A> = =0A> AFAIK, you never got back on why it was actually needed, instead of= =0A> directly calling these functions.=0A=0AIt is preparation for support= ing the other SoCs with THS as they have=0Aslightly different register la= youts and thus cannot be controlled by the=0Asame code.=0A=0A>> +/* Formu= la and parameters from the Allwinner 3.4 kernel */=0A>> +static int sun8i= _ths_reg_to_temperature(s32 reg, int divisor, int constant)=0A>> +{=0A>> = + return constant - (reg * 1000000) / divisor;=0A>> +}=0A>> +=0A>> +stati= c int sun8i_ths_get_temp(void *_data, int *out)=0A>> +{=0A>> + struct sun= 8i_ths_data *data =3D _data;=0A>> +=0A>> + return data->type->get_temp(da= ta, out);=0A>> +}=0A>> +=0A>> +static irqreturn_t sun8i_ths_irq_thread(in= t irq, void *_data)=0A>> +{=0A>> + struct sun8i_ths_data *data =3D _data;= =0A>> +=0A>> + data->type->irq(data);=0A>> + thermal_zone_device_update(d= ata->tzd);=0A>> +=0A>> + return IRQ_HANDLED;=0A>> +}=0A>> +=0A>> +static = int sun8i_ths_h3_init(struct platform_device *pdev,=0A>> + struct sun8i_t= hs_data *data)=0A>> +{=0A>> + int ret;=0A>> + size_t callen;=0A>> + s32 *= caldata;=0A>> +=0A>> + data->busclk =3D devm_clk_get(&pdev->dev, "ahb");= =0A>> + if (IS_ERR(data->busclk)) {=0A>> + ret =3D PTR_ERR(data->busclk);= =0A>> + dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret);=0A>> + r= eturn ret;=0A>> + }=0A>> +=0A>> + data->clk =3D devm_clk_get(&pdev->dev, = "ths");=0A>> + if (IS_ERR(data->clk)) {=0A>> + ret =3D PTR_ERR(data->clk)= ;=0A>> + dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret);=0A>> + = return ret;=0A>> + }=0A>> +=0A>> + data->reset =3D devm_reset_control_get= (&pdev->dev, "ahb");=0A>> + if (IS_ERR(data->reset)) {=0A>> + ret =3D PTR= _ERR(data->reset);=0A>> + dev_err(&pdev->dev, "failed to get reset: %d\n"= , ret);=0A>> + return ret;=0A>> + }=0A>> +=0A>> + if (data->calcell) {=0A= >> + caldata =3D nvmem_cell_read(data->calcell, &callen);=0A>> + if (IS_E= RR(caldata))=0A>> + return PTR_ERR(caldata);=0A>> + writel(be32_to_cpu(*c= aldata), data->regs + THS_H3_CDATA);=0A>> + kfree(caldata);=0A>> + }=0A>>= +=0A>> + ret =3D clk_prepare_enable(data->busclk);=0A>> + if (ret) {=0A>= > + dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret);=0A>> + re= turn ret;=0A>> + }=0A>> +=0A>> + ret =3D clk_prepare_enable(data->clk);= =0A>> + if (ret) {=0A>> + dev_err(&pdev->dev, "failed to enable ths clk: = %d\n", ret);=0A>> + goto err_disable_bus;=0A>> + }=0A>> +=0A>> + ret =3D = reset_control_deassert(data->reset);=0A>> + if (ret) {=0A>> + dev_err(&pd= ev->dev, "reset deassert failed: %d\n", ret);=0A>> + goto err_disable_ths= ;=0A>> + }=0A>> +=0A>> + /* The final sample period is calculated as foll= ows:=0A>> + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1)=0A>>= + *=0A>> + * This results to about 1Hz with these settings.=0A>> + */=0A= >> + ret =3D clk_set_rate(data->clk, 4000000);=0A> =0A> I don't follow yo= u here. You have a complicated math function, that=0A> has many input var= iables, and then, you just set the clock rate to a=0A> constant?=0A=0AHow= should this be handled then? I guess the sampling rate could=0Abe set in= the device tree and then the values calculated, but none=0Aof the other = thermal drivers seem to have configurable sample rate.=0A=0A>> + if (ret)= =0A>> + goto err_disable_ths;=0A> =0A> A new line here please=0A> =0A>> += writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE),=0A>> + = data->regs + THS_H3_CTRL0);=0A>> + writel(THS_H3_INT_CTRL_THERMAL_PER(THS= _H3_INT_CTRL_THERMAL_PER_VALUE) |=0A>> + THS_H3_INT_CTRL_DATA_IRQ_EN,=0A>= > + data->regs + THS_H3_INT_CTRL);=0A>> + writel(THS_H3_FILTER_EN | THS_H= 3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE),=0A>> + data->regs + THS_H3_FILTE= R);=0A>> + writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE= ) |=0A>> + THS_H3_CTRL2_SENSE_EN,=0A>> + data->regs + THS_H3_CTRL2);=0A> = =0A> And here too.=0A> =0A>> + return 0;=0A>> +=0A>> +err_disable_ths:=0A= >> + clk_disable_unprepare(data->clk);=0A>> +err_disable_bus:=0A>> + clk_= disable_unprepare(data->busclk);=0A>> +=0A>> + return ret;=0A>> +}=0A>> += =0A>> +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int = *out)=0A>> +{=0A>> + int val =3D readl(data->regs + THS_H3_DATA);=0A>> + = *out =3D sun8i_ths_reg_to_temperature(val, 8253, 217000);=0A>> + return 0= ;=0A> =0A> Can't you just return the value directly?=0A=0AI did that in t= he v1, clabbe.montjoie suggested to use temp variable to=0Aavoid column w= rap.=0A=0A>> +}=0A>> +=0A>> +static void sun8i_ths_h3_irq(struct sun8i_th= s_data *data)=0A>> +{=0A>> + writel(THS_H3_STAT_DATA_IRQ_STS |=0A>> + THS= _H3_STAT_ALARM_INT_STS |=0A>> + THS_H3_STAT_ALARM_OFF_STS |=0A>> + THS_H3= _STAT_SHUT_INT_STS,=0A>> + data->regs + THS_H3_STAT);=0A> =0A> So you're = always clearing all the interrupts? Shouldn't you just clear=0A> only the= interrupt you received?=0A> =0A>> +}=0A>> +=0A>> +static void sun8i_ths_= h3_deinit(struct sun8i_ths_data *data)=0A>> +{=0A>> + reset_control_asser= t(data->reset);=0A>> + clk_disable_unprepare(data->clk);=0A>> + clk_disab= le_unprepare(data->busclk);=0A>> +}=0A>> +=0A>> +static const struct ther= mal_zone_of_device_ops sun8i_ths_thermal_ops =3D {=0A>> + .get_temp =3D s= un8i_ths_get_temp,=0A>> +};=0A>> +=0A>> +static const struct sun8i_ths_ty= pe sun8i_ths_device_h3 =3D {=0A>> + .init =3D sun8i_ths_h3_init,=0A>> + .= get_temp =3D sun8i_ths_h3_get_temp,=0A>> + .irq =3D sun8i_ths_h3_irq,=0A>= > + .deinit =3D sun8i_ths_h3_deinit,=0A>> +};=0A>> +=0A>> +static const s= truct of_device_id sun8i_ths_id_table[] =3D {=0A>> + {=0A>> + .compatible= =3D "allwinner,sun8i-h3-ths",=0A>> + .data =3D &sun8i_ths_device_h3,=0A>= > + },=0A>> + {=0A>> + /* sentinel */=0A>> + },=0A>> +};=0A>> +MODULE_DEV= ICE_TABLE(of, sun8i_ths_id_table);=0A>> +=0A>> +static int sun8i_ths_prob= e(struct platform_device *pdev)=0A>> +{=0A>> + struct device_node *np =3D= pdev->dev.of_node;=0A>> + const struct of_device_id *match;=0A>> + struc= t sun8i_ths_data *data;=0A>> + struct resource *res;=0A>> + int ret;=0A>>= + int irq;=0A>> +=0A>> + match =3D of_match_node(sun8i_ths_id_table, np)= ;=0A> =0A> If you *really* need to (but I still don't really see why), yo= u can=0A> use of_device_get_match_data here.=0A> =0A>> +=0A>> + data =3D = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);=0A>> + if (!data)=0A= >> + return -ENOMEM;=0A>> +=0A>> + data->type =3D (struct sun8i_ths_type = *)match->data;=0A>> + data->pdev =3D pdev;=0A>> +=0A>> + data->calcell = =3D devm_nvmem_cell_get(&pdev->dev, "calibration");=0A>> + if (IS_ERR(dat= a->calcell)) {=0A>> + if (PTR_ERR(data->calcell) =3D=3D -EPROBE_DEFER)=0A= >> + return PTR_ERR(data->calcell);=0A> =0A> New line=0A> =0A>> + data->c= alcell =3D NULL; /* No calibration register */=0A> =0A> s/register/data/ = ?=0A> =0A>> + }=0A>> +=0A>> + res =3D platform_get_resource(pdev, IORESOU= RCE_MEM, 0);=0A>> + data->regs =3D devm_ioremap_resource(&pdev->dev, res)= ;=0A>> + if (IS_ERR(data->regs)) {=0A>> + ret =3D PTR_ERR(data->regs);=0A= >> + dev_err(&pdev->dev,=0A>> + "failed to ioremap THS registers: %d\n", = ret);=0A>> + return ret;=0A>> + }=0A>> +=0A>> + irq =3D platform_get_irq(= pdev, 0);=0A>> + if (irq < 0) {=0A>> + dev_err(&pdev->dev, "failed to get= IRQ: %d\n", irq);=0A>> + return irq;=0A>> + }=0A>> +=0A>> + ret =3D devm= _request_threaded_irq(&pdev->dev, irq, NULL,=0A>> + sun8i_ths_irq_thread,= IRQF_ONESHOT,=0A>> + dev_name(&pdev->dev), data);=0A> =0A> Why a threade= d irq?=0A=0AI thought threaded IRQs are preferred? Other thermal drivers= =0Ause them too. I am also not really sure thermal_zone_device_update()= =0Acan even be called in interrupt context.=0A=0A>> + if (ret)=0A>> + ret= urn ret;=0A>> +=0A>> + ret =3D data->type->init(pdev, data);=0A>> + if (r= et)=0A>> + return ret;=0A>> +=0A>> + data->tzd =3D thermal_zone_of_sensor= _register(&pdev->dev, 0, data,=0A>> + &sun8i_ths_thermal_ops);=0A>> + if = (IS_ERR(data->tzd)) {=0A>> + ret =3D PTR_ERR(data->tzd);=0A>> + dev_err(&= pdev->dev, "failed to register thermal zone: %d\n",=0A>> + ret);=0A>> + g= oto err_deinit;=0A>> + }=0A>> +=0A>> + platform_set_drvdata(pdev, data);= =0A>> + return 0;=0A>> +=0A>> +err_deinit:=0A>> + data->type->deinit(data= );=0A>> + return ret;=0A>> +}=0A>> +=0A>> +static int sun8i_ths_remove(st= ruct platform_device *pdev)=0A>> +{=0A>> + struct sun8i_ths_data *data = =3D platform_get_drvdata(pdev);=0A>> +=0A>> + thermal_zone_of_sensor_unre= gister(&pdev->dev, data->tzd);=0A>> + data->type->deinit(data);=0A>> + re= turn 0;=0A>> +}=0A>> +=0A>> +static struct platform_driver sun8i_ths_driv= er =3D {=0A>> + .probe =3D sun8i_ths_probe,=0A>> + .remove =3D sun8i_ths_= remove,=0A>> + .driver =3D {=0A>> + .name =3D "sun8i_ths",=0A>> + .of_mat= ch_table =3D sun8i_ths_id_table,=0A>> + },=0A>> +};=0A>> +=0A>> +module_p= latform_driver(sun8i_ths_driver);=0A>> +=0A>> +MODULE_AUTHOR("Josef Gajdu= sek ");=0A>> +MODULE_DESCRIPTION("Sunxi THS driver");=0A> = =0A> Please change the description here too to match the header.=0A> =0A>= Thanks!=0A> Maxime=0A> =0A> --=0A> Maxime Ripard, Free Electrons=0A> Emb= edded Linux, Kernel and Android engineering=0A> http://free-electrons.com= =0A> =0A> --=0A> You received this message because you are subscribed to = the Google Groups "linux-sunxi" group.=0A> To unsubscribe from this group= and stop receiving emails from it, send an email to=0A> linux-sunxi+unsu= bscribe@googlegroups.com.=0A> For more options, visit https://groups.goog= le.com/d/optout.=0A=0A=0AJosef Gajdusek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 1 Dec 2015 09:41:17 +0100 From: Maxime Ripard To: Shuge Cc: linux-sunxi , atx@atx.name, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org Subject: Re: [linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Message-ID: <20151201084117.GB29263@lukather> References: <20151123124356.GW32142@lukather> <20151124093202.GL32142@lukather> <56550D70.6060109@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="PmA2V3Z32TCmWXqI" In-Reply-To: <56550D70.6060109@gmail.com> List-ID: --PmA2V3Z32TCmWXqI Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Wed, Nov 25, 2015 at 09:22:56AM +0800, Shuge wrote: > On Monday, November 23, 2015 at 17:32 UTC+8, Maxime Ripard wrote: > > On Mon, Nov 23, 2015 at 10:51:15PM -0800, Sugar Wu wrote: > >> On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: > >>> > >>> Hi,=20 > >>> > >>> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:=20 > >>>> Add a node describing the Security ID memory to the=20 > >>>> Allwinner H3 .dtsi file.=20 > >>>> > >>>> Signed-off-by: Josef Gajdusek >=20 > >>>> ---=20 > >>>> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++=20 > >>>> 1 file changed, 7 insertions(+)=20 > >>>> > >>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi=20 > >>> b/arch/arm/boot/dts/sun8i-h3.dtsi=20 > >>>> index 0faa38a..58de718 100644=20 > >>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi=20 > >>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi=20 > >>>> @@ -359,6 +359,13 @@=20 > >>>> #size-cells =3D <0>;=20 > >>>> };=20 > >>>> =20 > >>>> + sid: eeprom@01c14000 {=20 > >>>> + compatible =3D "allwinner,sun4i-a10-sid";= =20 > >>>> + reg =3D <0x01c14000 0x400>;=20 > >>> > >>> The datasheet says it's 256 bytes wide, while the size here is of 1kB= ,=20 > >>> is it intentional?=20 > >> > >> SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse spac= e. > >> H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. > >=20 > > Interesting, what is below the 0x200 registers? > > > Some control register about SID. > offset: 0x40 SID Program/Read Control Register > offset: 0x50 SID Program Key Value Register > offset: 0x60 SID Read Key Value Register > offset: 0x70 \ > offset: 0x80 SJTAG Attribute 0 Register > offset: 0x84 SJTAG Attribute 1 Register > offset: 0x88 SJTAG Select Register > offset: 0x90 SID Program Ctrol register for burned timing Thanks! I guess the layout changed a bit from the A10 and alikes then. Anyway, we should expose only to the nvmem framework the actual eeprom space, so from 0x200 to 0x300 from what you're saying (just like we should only expose the first 4 bytes in the A10 / A20) Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --PmA2V3Z32TCmWXqI Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWXV0tAAoJEBx+YmzsjxAggPYP/3SmveWMuEu6JtVlbazbg5k2 tn8HKMKVSleaQsEYjrF/4+zQK+5jZC9ZuszIP0M3N7Fqa/KMXhYOwTTFMWHSWMdk ur2wnL4LGwWUs9GXFIfCXD/5BVGn3ceWLU3EfXtACnCHKj8hJvneD1Oulx1pC2Hr dJNnCFqK8cNH6Tvff/W8S92z8YJqfnbqH+o8q2NBukRtL3U+hCZmZyi/Etpzzlr4 8mjrcs7c72sTXMKAF7/8nh2nA+DYIgQ29xtsSr7+XtWdr8x6FWt1FRIDhPElhkQO rGQSw7amdXNb9DOz3gHTqLD6+tkazeeXyp0SvKqrSCQYyF8DnW+l+TH6cFZjpirQ VyH5FAV9+hEi80aAHX1TsKoxBlx9WOJ+TeXU3kndWxfCHvHWVBgmC2HGOzN1E11+ hkPfigQdzd436kYg+pfMoOFnr/YMEwAk7FUUIYMpYHml7KrpeHq+IMDDSY5Ixzl9 ZRYCEpSZJW5dl4WSk9F1maqqjXbnP8zxm2SAfFk67tMFLj92XUDERSgWpeenX0v/ w4+BphRKFr5EdOZuD3A6D+pnykdoUBMn/5HhVP+vQXxMAQB9shfBhjOsks75sxZw LEt8Ks9Avb5YS3zB437Biw8TDuBquxUtR2iWA7LXlB4zEg+/m+J0FzK6zstQzgn3 sIZsmoiMV5ts4y127RiW =Lely -----END PGP SIGNATURE----- --PmA2V3Z32TCmWXqI-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Josef Gajdusek Subject: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Mon, 23 Nov 2015 09:02:48 +0100 Message-ID: References: Reply-To: atx-MwjtXicnQwU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: In-Reply-To: References: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Cc: Josef Gajdusek , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org Add a node describing the Security ID memory to the Allwinner H3 .dtsi file. Signed-off-by: Josef Gajdusek --- arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 0faa38a..58de718 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -359,6 +359,13 @@ #size-cells = <0>; }; + sid: eeprom@01c14000 { + compatible = "allwinner,sun4i-a10-sid"; + reg = <0x01c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + usbphy: phy@01c19400 { compatible = "allwinner,sun8i-h3-usb-phy"; reg = <0x01c19400 0x2c>, -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Josef Gajdusek Subject: [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock Date: Mon, 23 Nov 2015 09:02:49 +0100 Message-ID: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> References: Reply-To: atx-MwjtXicnQwU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: In-Reply-To: References: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Cc: Josef Gajdusek , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org This patch adds a driver for the THS clock which is present on the Allwinner H3. Signed-off-by: Josef Gajdusek --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-h3-ths.c | 98 +++++++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/clk/sunxi/clk-h3-ths.c diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 23e7bce..6d63b35 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -73,6 +73,7 @@ Required properties: "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 + "allwinner,sun8i-h3-ths-clk" - for THS on H3 Required properties for all clocks: - reg : shall be the control register address for the clock. diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index f520af6..1bf8e1c 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -8,6 +8,7 @@ obj-y += clk-a10-hosc.o obj-y += clk-a10-mod1.o obj-y += clk-a10-pll2.o obj-y += clk-a20-gmac.o +obj-y += clk-h3-ths.o obj-y += clk-mod0.o obj-y += clk-simple-gates.o obj-y += clk-sun8i-bus-gates.o diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk-h3-ths.c new file mode 100644 index 0000000..663afc0 --- /dev/null +++ b/drivers/clk/sunxi/clk-h3-ths.c @@ -0,0 +1,98 @@ +/* + * Sunxi THS clock driver + * + * Copyright (C) 2015 Josef Gajdusek + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#define SUN8I_H3_THS_CLK_ENABLE 31 +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0 +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2 + +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock); + +static const struct clk_div_table sun8i_h3_ths_clk_table[] __initconst = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 6 }, + { } /* sentinel */ +}; + +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) +{ + struct clk *clk; + struct clk_gate *gate; + struct clk_divider *div; + const char *parent; + const char *clk_name = node->name; + void __iomem *reg; + int err; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + + if (IS_ERR(reg)) + return; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto err_unmap; + + div = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!div) + goto err_gate_free; + + of_property_read_string(node, "clock-output-names", &clk_name); + parent = of_clk_get_parent_name(node, 0); + + gate->reg = reg; + gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE; + gate->lock = &sun8i_h3_ths_clk_lock; + + div->reg = reg; + div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT; + div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH; + div->table = sun8i_h3_ths_clk_table; + div->lock = &sun8i_h3_ths_clk_lock; + + clk = clk_register_composite(NULL, clk_name, &parent, 1, + NULL, NULL, + &div->hw, &clk_divider_ops, + &gate->hw, &clk_gate_ops, + CLK_SET_RATE_PARENT); + + if (IS_ERR(clk)) + goto err_div_free; + + err = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (err) + goto err_unregister_clk; + + return; + +err_unregister_clk: + clk_unregister(clk); +err_gate_free: + kfree(gate); +err_div_free: + kfree(div); +err_unmap: + iounmap(reg); +} + +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk", + sun8i_h3_ths_clk_setup); -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Josef Gajdusek Subject: [PATCH v2 0/5] sunxi: THS support Date: Mon, 23 Nov 2015 09:02:47 +0100 Message-ID: Reply-To: atx-MwjtXicnQwU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Cc: Josef Gajdusek , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org Hello everyone, this is v2 of my THS patchset Changelog: * Some stylistic changes * devm_reset_control_get_optional -> devm_reset_control_get * Added the clk-h3-ths clock driver - Note: A23/A33/A83T do not have a separate clock, H3 seems to be the first (and only?) SoC with it - Because of this, I moved the clock init code to the H3-specific init function. * Use the nvmem cell abstraction instead of accessing the configuration memory directly * Use the IRQ line (and fixed incorrect interrupt number in the DTS) * Renamed to sun8i_ths Ad the "magical constants": what I meant is that altough the datasheet explains what they are, it does not explain how to pick their values. "ADC" and "Sensor" "acquire time" are also not exactly the most helpful descriptions. Anyway, I changed the values such as the final sampling rate is about 1Hz. Josef Gajdusek (5): ARM: dts: sun8i: Add SID node clk: sunxi: Add driver for the H3 THS clock thermal: Add a driver for the Allwinner THS sensor dt-bindings: document sun8i_ths ARM: dts: sun8i: Add THS node to the H3 .dtsi Documentation/devicetree/bindings/clock/sunxi.txt | 1 + .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++ arch/arm/boot/dts/sun8i-h3.dtsi | 40 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-h3-ths.c | 98 ++++++ drivers/thermal/Kconfig | 7 + drivers/thermal/Makefile | 1 + drivers/thermal/sun8i_ths.c | 365 +++++++++++++++++++++ 8 files changed, 544 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt create mode 100644 drivers/clk/sunxi/clk-h3-ths.c create mode 100644 drivers/thermal/sun8i_ths.c -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Josef Gajdusek Subject: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor Date: Mon, 23 Nov 2015 09:02:50 +0100 Message-ID: References: Reply-To: atx-MwjtXicnQwU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: In-Reply-To: References: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Cc: Josef Gajdusek , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org This patch adds support for the Sunxi thermal sensor on the Allwinner H3. Should be easily extendable for the A33/A83T/... as they have similar but not completely identical sensors. Signed-off-by: Josef Gajdusek --- drivers/thermal/Kconfig | 7 + drivers/thermal/Makefile | 1 + drivers/thermal/sun8i_ths.c | 365 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 373 insertions(+) create mode 100644 drivers/thermal/sun8i_ths.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index c463c89..2b41147 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config SUN8I_THS + tristate "sun8i THS driver" + depends on MACH_SUN8I + depends on OF + help + Enable this to support thermal reporting on some newer Allwinner SoCs. + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index cfae6a6..227e1a1 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_SUN8I_THS) += sun8i_ths.o diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c new file mode 100644 index 0000000..2c976ac --- /dev/null +++ b/drivers/thermal/sun8i_ths.c @@ -0,0 +1,365 @@ +/* + * Sunxi THS driver + * + * Copyright (C) 2015 Josef Gajdusek + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define THS_H3_CTRL0 0x00 +#define THS_H3_CTRL1 0x04 +#define THS_H3_CDAT 0x14 +#define THS_H3_CTRL2 0x40 +#define THS_H3_INT_CTRL 0x44 +#define THS_H3_STAT 0x48 +#define THS_H3_ALARM_CTRL 0x50 +#define THS_H3_SHUTDOWN_CTRL 0x60 +#define THS_H3_FILTER 0x70 +#define THS_H3_CDATA 0x74 +#define THS_H3_DATA 0x80 + +#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS 0 +#define THS_H3_CTRL0_SENSOR_ACQ0(x) \ + ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS) +#define THS_H3_CTRL1_ADC_CALI_EN_OFFS 17 +#define THS_H3_CTRL1_ADC_CALI_EN \ + BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS) +#define THS_H3_CTRL1_OP_BIAS_OFFS 20 +#define THS_H3_CTRL1_OP_BIAS(x) \ + ((x) << THS_H3_CTRL1_OP_BIAS_OFFS) +#define THS_H3_CTRL2_SENSE_EN_OFFS 0 +#define THS_H3_CTRL2_SENSE_EN \ + BIT(THS_H3_CTRL2_SENSE_EN_OFFS) +#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS 16 +#define THS_H3_CTRL2_SENSOR_ACQ1(x) \ + ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS) + +#define THS_H3_INT_CTRL_ALARM_INT_EN_OFFS 0 +#define THS_H3_INT_CTRL_ALARM_INT_EN \ + BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS) +#define THS_H3_INT_CTRL_SHUT_INT_EN_OFFS 4 +#define THS_H3_INT_CTRL_SHUT_INT_EN \ + BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS) +#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS 8 +#define THS_H3_INT_CTRL_DATA_IRQ_EN \ + BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS) +#define THS_H3_INT_CTRL_THERMAL_PER_OFFS 12 +#define THS_H3_INT_CTRL_THERMAL_PER(x) \ + ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS) + +#define THS_H3_STAT_ALARM_INT_STS_OFFS 0 +#define THS_H3_STAT_ALARM_INT_STS \ + BIT(THS_H3_STAT_ALARM_INT_STS_OFFS) +#define THS_H3_STAT_SHUT_INT_STS_OFFS 4 +#define THS_H3_STAT_SHUT_INT_STS \ + BIT(THS_H3_STAT_SHUT_INT_STS_OFFS) +#define THS_H3_STAT_DATA_IRQ_STS_OFFS 8 +#define THS_H3_STAT_DATA_IRQ_STS \ + BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS) +#define THS_H3_STAT_ALARM_OFF_STS_OFFS 12 +#define THS_H3_STAT_ALARM_OFF_STS \ + BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS) + +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS 0 +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST(x) \ + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS) +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS 16 +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT(x) \ + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS) + +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS 16 +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT(x) \ + ((x) << THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS) + +#define THS_H3_FILTER_TYPE_OFFS 0 +#define THS_H3_FILTER_TYPE(x) \ + ((x) << THS_H3_FILTER_TYPE_OFFS) +#define THS_H3_FILTER_EN_OFFS 2 +#define THS_H3_FILTER_EN \ + BIT(THS_H3_FILTER_EN_OFFS) + +#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0xff +#define THS_H3_INT_CTRL_THERMAL_PER_VALUE 0x79 +#define THS_H3_FILTER_TYPE_VALUE 0x2 +#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f + +struct sun8i_ths_data { + struct sun8i_ths_type *type; + struct reset_control *reset; + struct clk *clk; + struct clk *busclk; + void __iomem *regs; + struct nvmem_cell *calcell; + struct platform_device *pdev; + struct thermal_zone_device *tzd; +}; + +struct sun8i_ths_type { + int (*init)(struct platform_device *, struct sun8i_ths_data *); + int (*get_temp)(struct sun8i_ths_data *, int *out); + void (*irq)(struct sun8i_ths_data *); + void (*deinit)(struct sun8i_ths_data *); +}; + +/* Formula and parameters from the Allwinner 3.4 kernel */ +static int sun8i_ths_reg_to_temperature(s32 reg, int divisor, int constant) +{ + return constant - (reg * 1000000) / divisor; +} + +static int sun8i_ths_get_temp(void *_data, int *out) +{ + struct sun8i_ths_data *data = _data; + + return data->type->get_temp(data, out); +} + +static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data) +{ + struct sun8i_ths_data *data = _data; + + data->type->irq(data); + thermal_zone_device_update(data->tzd); + + return IRQ_HANDLED; +} + +static int sun8i_ths_h3_init(struct platform_device *pdev, + struct sun8i_ths_data *data) +{ + int ret; + size_t callen; + s32 *caldata; + + data->busclk = devm_clk_get(&pdev->dev, "ahb"); + if (IS_ERR(data->busclk)) { + ret = PTR_ERR(data->busclk); + dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret); + return ret; + } + + data->clk = devm_clk_get(&pdev->dev, "ths"); + if (IS_ERR(data->clk)) { + ret = PTR_ERR(data->clk); + dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret); + return ret; + } + + data->reset = devm_reset_control_get(&pdev->dev, "ahb"); + if (IS_ERR(data->reset)) { + ret = PTR_ERR(data->reset); + dev_err(&pdev->dev, "failed to get reset: %d\n", ret); + return ret; + } + + if (data->calcell) { + caldata = nvmem_cell_read(data->calcell, &callen); + if (IS_ERR(caldata)) + return PTR_ERR(caldata); + writel(be32_to_cpu(*caldata), data->regs + THS_H3_CDATA); + kfree(caldata); + } + + ret = clk_prepare_enable(data->busclk); + if (ret) { + dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(data->clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret); + goto err_disable_bus; + } + + ret = reset_control_deassert(data->reset); + if (ret) { + dev_err(&pdev->dev, "reset deassert failed: %d\n", ret); + goto err_disable_ths; + } + + /* The final sample period is calculated as follows: + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) + * + * This results to about 1Hz with these settings. + */ + ret = clk_set_rate(data->clk, 4000000); + if (ret) + goto err_disable_ths; + writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE), + data->regs + THS_H3_CTRL0); + writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) | + THS_H3_INT_CTRL_DATA_IRQ_EN, + data->regs + THS_H3_INT_CTRL); + writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE), + data->regs + THS_H3_FILTER); + writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) | + THS_H3_CTRL2_SENSE_EN, + data->regs + THS_H3_CTRL2); + return 0; + +err_disable_ths: + clk_disable_unprepare(data->clk); +err_disable_bus: + clk_disable_unprepare(data->busclk); + + return ret; +} + +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *out) +{ + int val = readl(data->regs + THS_H3_DATA); + *out = sun8i_ths_reg_to_temperature(val, 8253, 217000); + return 0; +} + +static void sun8i_ths_h3_irq(struct sun8i_ths_data *data) +{ + writel(THS_H3_STAT_DATA_IRQ_STS | + THS_H3_STAT_ALARM_INT_STS | + THS_H3_STAT_ALARM_OFF_STS | + THS_H3_STAT_SHUT_INT_STS, + data->regs + THS_H3_STAT); +} + +static void sun8i_ths_h3_deinit(struct sun8i_ths_data *data) +{ + reset_control_assert(data->reset); + clk_disable_unprepare(data->clk); + clk_disable_unprepare(data->busclk); +} + +static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = { + .get_temp = sun8i_ths_get_temp, +}; + +static const struct sun8i_ths_type sun8i_ths_device_h3 = { + .init = sun8i_ths_h3_init, + .get_temp = sun8i_ths_h3_get_temp, + .irq = sun8i_ths_h3_irq, + .deinit = sun8i_ths_h3_deinit, +}; + +static const struct of_device_id sun8i_ths_id_table[] = { + { + .compatible = "allwinner,sun8i-h3-ths", + .data = &sun8i_ths_device_h3, + }, + { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, sun8i_ths_id_table); + +static int sun8i_ths_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + struct sun8i_ths_data *data; + struct resource *res; + int ret; + int irq; + + match = of_match_node(sun8i_ths_id_table, np); + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->type = (struct sun8i_ths_type *)match->data; + data->pdev = pdev; + + data->calcell = devm_nvmem_cell_get(&pdev->dev, "calibration"); + if (IS_ERR(data->calcell)) { + if (PTR_ERR(data->calcell) == -EPROBE_DEFER) + return PTR_ERR(data->calcell); + data->calcell = NULL; /* No calibration register */ + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->regs)) { + ret = PTR_ERR(data->regs); + dev_err(&pdev->dev, + "failed to ioremap THS registers: %d\n", ret); + return ret; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); + return irq; + } + + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, + sun8i_ths_irq_thread, IRQF_ONESHOT, + dev_name(&pdev->dev), data); + if (ret) + return ret; + + ret = data->type->init(pdev, data); + if (ret) + return ret; + + data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, + &sun8i_ths_thermal_ops); + if (IS_ERR(data->tzd)) { + ret = PTR_ERR(data->tzd); + dev_err(&pdev->dev, "failed to register thermal zone: %d\n", + ret); + goto err_deinit; + } + + platform_set_drvdata(pdev, data); + return 0; + +err_deinit: + data->type->deinit(data); + return ret; +} + +static int sun8i_ths_remove(struct platform_device *pdev) +{ + struct sun8i_ths_data *data = platform_get_drvdata(pdev); + + thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); + data->type->deinit(data); + return 0; +} + +static struct platform_driver sun8i_ths_driver = { + .probe = sun8i_ths_probe, + .remove = sun8i_ths_remove, + .driver = { + .name = "sun8i_ths", + .of_match_table = sun8i_ths_id_table, + }, +}; + +module_platform_driver(sun8i_ths_driver); + +MODULE_AUTHOR("Josef Gajdusek "); +MODULE_DESCRIPTION("Sunxi THS driver"); +MODULE_LICENSE("GPL v2"); -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Josef Gajdusek Subject: [PATCH v2 4/5] dt-bindings: document sun8i_ths Date: Mon, 23 Nov 2015 09:02:51 +0100 Message-ID: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> References: Reply-To: atx-MwjtXicnQwU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: In-Reply-To: References: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Cc: Josef Gajdusek , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org This patch adds the binding documentation for the sun8i_ths driver Signed-off-by: Josef Gajdusek --- .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt new file mode 100644 index 0000000..67056bf --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt @@ -0,0 +1,31 @@ +* sun8i THS + +Required properties: +- compatible : "allwinner,sun8i-h3-ths" +- reg : Address range of the thermal registers and location of the calibration + value +- resets : Must contain an entry for each entry in reset-names. + see ../reset/reset.txt for details +- reset-names : Must include the name "ahb" +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS + clock + +Optional properties: +- nvmem-cells : Must contain an entry for each entry in nvmem-cell-names +- nvmem-cell-names : Must contain "calibration" for the cell containing the + temperature calibration cell, if available + +Example: +ths: ths@01c25000 { + #thermal-sensor-cells = <0>; + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x88>, <0x01c14234 0x4>; + interrupts = ; + resets = <&bus_rst 136>; + reset-names = "ahb"; + clocks = <&bus_gates 72>, <&ths_clk>; + clock-names = "ahb", "ths"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; +}; -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Josef Gajdusek Subject: [PATCH v2 5/5] ARM: dts: sun8i: Add THS node to the H3 .dtsi Date: Mon, 23 Nov 2015 09:02:52 +0100 Message-ID: <0fff612e26bf9cda9027a4175e16d25a0c2cc62c.1448263428.git.atx@atx.name> References: Reply-To: atx-MwjtXicnQwU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: In-Reply-To: References: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Cc: Josef Gajdusek , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org This patch adds nodes for the THS driver and the THS clock to the Allwinner H3 .dtsi file. Signed-off-by: Josef Gajdusek --- arch/arm/boot/dts/sun8i-h3.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 58de718..48500d4 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -77,6 +77,14 @@ }; }; + thermal-zones { + cpu_thermal: cpu_thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 0>; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -236,6 +244,14 @@ "ahb1_ephy", "ahb1_dbg"; }; + ths_clk: clk@01c20074 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ths-clk"; + reg = <0x01c20074 0x4>; + clocks = <&osc24M>; + clock-output-names = "ths"; + }; + mmc0_clk: clk@01c20088 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; @@ -364,6 +380,10 @@ reg = <0x01c14000 0x400>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: calib@234 { + reg = <0x234 0x4>; + }; }; usbphy: phy@01c19400 { @@ -529,6 +549,19 @@ interrupts = ; }; + ths: ths@01c25000 { + #thermal-sensor-cells = <0>; + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x88>; + interrupts = ; + resets = <&bus_rst 104>; + reset-names = "ahb"; + clocks = <&bus_gates 72>, <&ths_clk>; + clock-names = "ahb", "ths"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chen-Yu Tsai Subject: Re: [PATCH v2 4/5] dt-bindings: document sun8i_ths Date: Mon, 23 Nov 2015 17:47:11 +0800 Message-ID: References: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> Reply-To: wens-jdAy2FN1RRM@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx-MwjtXicnQwU@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Josef Gajdusek Cc: linux-sunxi , linux-clk , linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel , linux-arm-kernel , devicetree , gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, Mike Turquette , Hans De Goede , Stephen Boyd , Michael Turquette , Emilio Lopez , Russell King - ARM Linux , Eduardo Valentin , Zhang Rui , Chen-Yu Tsai , Maxime Ripard , Kumar Gala , Ian Campbell , Mark Rutland , Pawel Moll , Rob Herring List-Id: linux-pm@vger.kernel.org On Mon, Nov 23, 2015 at 4:02 PM, Josef Gajdusek wrote: > This patch adds the binding documentation for the sun8i_ths driver > > Signed-off-by: Josef Gajdusek > --- > .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt > > diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > new file mode 100644 > index 0000000..67056bf > --- /dev/null > +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > @@ -0,0 +1,31 @@ > +* sun8i THS > + > +Required properties: > +- compatible : "allwinner,sun8i-h3-ths" > +- reg : Address range of the thermal registers and location of the calibration > + value You are now using nvmem for the calibration data. You don't need the second entry. > +- resets : Must contain an entry for each entry in reset-names. > + see ../reset/reset.txt for details > +- reset-names : Must include the name "ahb" > +- clocks : Must contain an entry for each entry in clock-names. > +- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS > + clock > + > +Optional properties: > +- nvmem-cells : Must contain an entry for each entry in nvmem-cell-names > +- nvmem-cell-names : Must contain "calibration" for the cell containing the > + temperature calibration cell, if available > + > +Example: > +ths: ths@01c25000 { > + #thermal-sensor-cells = <0>; > + compatible = "allwinner,sun8i-h3-ths"; > + reg = <0x01c25000 0x88>, <0x01c14234 0x4>; Same here. ChenYu > + interrupts = ; > + resets = <&bus_rst 136>; > + reset-names = "ahb"; > + clocks = <&bus_gates 72>, <&ths_clk>; > + clock-names = "ahb", "ths"; > + nvmem-cells = <&ths_calibration>; > + nvmem-cell-names = "calibration"; > +}; > -- > 2.4.10 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Priit Laes Subject: Re: [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock Date: Mon, 23 Nov 2015 12:28:09 +0200 Message-ID: <1448274489.27496.1.camel@plaes.org> References: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> Reply-To: plaes-q/aMd4JkU83YtjvyW6yDsg@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx-MwjtXicnQwU@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: atx-MwjtXicnQwU@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org On Mon, 2015-11-23 at 09:02 +0100, Josef Gajdusek wrote: > This patch adds a driver for the THS clock which is present on the > Allwinner H3. >=20 > Signed-off-by: Josef Gajdusek > --- > =C2=A0Documentation/devicetree/bindings/clock/sunxi.txt |=C2=A0=C2=A01 + > =C2=A0drivers/clk/sunxi/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A01 + > =C2=A0drivers/clk/sunxi/clk-h3-ths.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0| 98 > +++++++++++++++++++++++ > =C2=A03 files changed, 100 insertions(+) > =C2=A0create mode 100644 drivers/clk/sunxi/clk-h3-ths.c >=20 > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt > b/Documentation/devicetree/bindings/clock/sunxi.txt > index 23e7bce..6d63b35 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -73,6 +73,7 @@ Required properties: > =C2=A0 "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 > =C2=A0 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets > on A80 > =C2=A0 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + > resets on A80 > + "allwinner,sun8i-h3-ths-clk" - for THS on H3 > =C2=A0 > =C2=A0Required properties for all clocks: > =C2=A0- reg : shall be the control register address for the clock. > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index f520af6..1bf8e1c 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -8,6 +8,7 @@ obj-y +=3D clk-a10-hosc.o > =C2=A0obj-y +=3D clk-a10-mod1.o > =C2=A0obj-y +=3D clk-a10-pll2.o > =C2=A0obj-y +=3D clk-a20-gmac.o > +obj-y +=3D clk-h3-ths.o > =C2=A0obj-y +=3D clk-mod0.o > =C2=A0obj-y +=3D clk-simple-gates.o > =C2=A0obj-y +=3D clk-sun8i-bus-gates.o > diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk- > h3-ths.c > new file mode 100644 > index 0000000..663afc0 > --- /dev/null > +++ b/drivers/clk/sunxi/clk-h3-ths.c > @@ -0,0 +1,98 @@ > +/* > + * Sunxi THS clock driver This should be "Allwinner H3 THS clock driver" > + * > + * Copyright (C) 2015 Josef Gajdusek > + * > + * This software is licensed under the terms of the GNU General > Public > + * License version 2, as published by the Free Software Foundation, > and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > + > +#define SUN8I_H3_THS_CLK_ENABLE 31 > +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0 > +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2 > + > +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock); > + > +static const struct clk_div_table sun8i_h3_ths_clk_table[] > __initconst =3D { > + { .val =3D 0, .div =3D 1 }, > + { .val =3D 1, .div =3D 2 }, > + { .val =3D 2, .div =3D 4 }, > + { .val =3D 3, .div =3D 6 }, > + { } /* sentinel */ > +}; > + > +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) > +{ > + struct clk *clk; > + struct clk_gate *gate; > + struct clk_divider *div; > + const char *parent; > + const char *clk_name =3D node->name; > + void __iomem *reg; > + int err; > + > + reg =3D of_io_request_and_map(node, 0, > of_node_full_name(node)); > + > + if (IS_ERR(reg)) > + return; > + > + gate =3D kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!gate) > + goto err_unmap; > + > + div =3D kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!div) > + goto err_gate_free; > + > + of_property_read_string(node, "clock-output-names", > &clk_name); > + parent =3D of_clk_get_parent_name(node, 0); > + > + gate->reg =3D reg; > + gate->bit_idx =3D SUN8I_H3_THS_CLK_ENABLE; > + gate->lock =3D &sun8i_h3_ths_clk_lock; > + > + div->reg =3D reg; > + div->shift =3D SUN8I_H3_THS_CLK_DIVIDER_SHIFT; > + div->width =3D SUN8I_H3_THS_CLK_DIVIDER_WIDTH; > + div->table =3D sun8i_h3_ths_clk_table; > + div->lock =3D &sun8i_h3_ths_clk_lock; > + > + clk =3D clk_register_composite(NULL, clk_name, &parent, 1, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0NULL, NULL, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0&div->hw, &clk_divider_ops, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0&gate->hw, &clk_gate_ops, > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0CLK_SET_RATE_PARENT); > + > + if (IS_ERR(clk)) > + goto err_div_free; > + > + err =3D of_clk_add_provider(node, of_clk_src_simple_get, clk); > + if (err) > + goto err_unregister_clk; > + > + return; > + > +err_unregister_clk: > + clk_unregister(clk); > +err_gate_free: > + kfree(gate); > +err_div_free: > + kfree(div); > +err_unmap: > + iounmap(reg); > +} > + > +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk", > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0sun8i_h3_ths_clk_setup); > --=20 > 2.4.10 >=20 --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. 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From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v2 4/5] dt-bindings: document sun8i_ths Date: Mon, 23 Nov 2015 13:38:37 +0100 Message-ID: <20151123123837.GV32142@lukather> References: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Fh5LqGQwq8YwuKb/" Return-path: Content-Disposition: inline In-Reply-To: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx-MwjtXicnQwU@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Josef Gajdusek Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org --Fh5LqGQwq8YwuKb/ Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Hi, On Mon, Nov 23, 2015 at 09:02:51AM +0100, Josef Gajdusek wrote: > This patch adds the binding documentation for the sun8i_ths driver > > Signed-off-by: Josef Gajdusek > --- > .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt > > diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > new file mode 100644 > index 0000000..67056bf > --- /dev/null > +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > @@ -0,0 +1,31 @@ > +* sun8i THS > + > +Required properties: > +- compatible : "allwinner,sun8i-h3-ths" > +- reg : Address range of the thermal registers and location of the calibration > + value > +- resets : Must contain an entry for each entry in reset-names. > + see ../reset/reset.txt for details > +- reset-names : Must include the name "ahb" If you have a single reset line, you don't need reset-names. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --Fh5LqGQwq8YwuKb/-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Mon, 23 Nov 2015 13:43:56 +0100 Message-ID: <20151123124356.GW32142@lukather> References: Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="1lE8Wy7Exphh2Vpg" Return-path: Content-Disposition: inline In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Josef Gajdusek Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org --1lE8Wy7Exphh2Vpg Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Hi, On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > Add a node describing the Security ID memory to the > Allwinner H3 .dtsi file. > > Signed-off-by: Josef Gajdusek > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > index 0faa38a..58de718 100644 > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -359,6 +359,13 @@ > #size-cells = <0>; > }; > > + sid: eeprom@01c14000 { > + compatible = "allwinner,sun4i-a10-sid"; > + reg = <0x01c14000 0x400>; The datasheet says it's 256 bytes wide, while the size here is of 1kB, is it intentional? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --1lE8Wy7Exphh2Vpg-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock Date: Mon, 23 Nov 2015 15:37:08 -0600 Message-ID: <20151123213708.GA12308@rob-hp-laptop> References: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> Reply-To: robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Content-Disposition: inline In-Reply-To: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx-MwjtXicnQwU@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Josef Gajdusek Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org List-Id: linux-pm@vger.kernel.org On Mon, Nov 23, 2015 at 09:02:49AM +0100, Josef Gajdusek wrote: > This patch adds a driver for the THS clock which is present on the > Allwinner H3. > > Signed-off-by: Josef Gajdusek Acked-by: Rob Herring > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk-h3-ths.c | 98 +++++++++++++++++++++++ > 3 files changed, 100 insertions(+) > create mode 100644 drivers/clk/sunxi/clk-h3-ths.c > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > index 23e7bce..6d63b35 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -73,6 +73,7 @@ Required properties: > "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 > "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 > "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 > + "allwinner,sun8i-h3-ths-clk" - for THS on H3 > > Required properties for all clocks: > - reg : shall be the control register address for the clock. > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index f520af6..1bf8e1c 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -8,6 +8,7 @@ obj-y += clk-a10-hosc.o > obj-y += clk-a10-mod1.o > obj-y += clk-a10-pll2.o > obj-y += clk-a20-gmac.o > +obj-y += clk-h3-ths.o > obj-y += clk-mod0.o > obj-y += clk-simple-gates.o > obj-y += clk-sun8i-bus-gates.o > diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk-h3-ths.c > new file mode 100644 > index 0000000..663afc0 > --- /dev/null > +++ b/drivers/clk/sunxi/clk-h3-ths.c > @@ -0,0 +1,98 @@ > +/* > + * Sunxi THS clock driver > + * > + * Copyright (C) 2015 Josef Gajdusek > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > + > +#define SUN8I_H3_THS_CLK_ENABLE 31 > +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0 > +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2 > + > +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock); > + > +static const struct clk_div_table sun8i_h3_ths_clk_table[] __initconst = { > + { .val = 0, .div = 1 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 6 }, > + { } /* sentinel */ > +}; > + > +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) > +{ > + struct clk *clk; > + struct clk_gate *gate; > + struct clk_divider *div; > + const char *parent; > + const char *clk_name = node->name; > + void __iomem *reg; > + int err; > + > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > + > + if (IS_ERR(reg)) > + return; > + > + gate = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!gate) > + goto err_unmap; > + > + div = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!div) > + goto err_gate_free; > + > + of_property_read_string(node, "clock-output-names", &clk_name); > + parent = of_clk_get_parent_name(node, 0); > + > + gate->reg = reg; > + gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE; > + gate->lock = &sun8i_h3_ths_clk_lock; > + > + div->reg = reg; > + div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT; > + div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH; > + div->table = sun8i_h3_ths_clk_table; > + div->lock = &sun8i_h3_ths_clk_lock; > + > + clk = clk_register_composite(NULL, clk_name, &parent, 1, > + NULL, NULL, > + &div->hw, &clk_divider_ops, > + &gate->hw, &clk_gate_ops, > + CLK_SET_RATE_PARENT); > + > + if (IS_ERR(clk)) > + goto err_div_free; > + > + err = of_clk_add_provider(node, of_clk_src_simple_get, clk); > + if (err) > + goto err_unregister_clk; > + > + return; > + > +err_unregister_clk: > + clk_unregister(clk); > +err_gate_free: > + kfree(gate); > +err_div_free: > + kfree(div); > +err_unmap: > + iounmap(reg); > +} > + > +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk", > + sun8i_h3_ths_clk_setup); > -- > 2.4.10 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chen-Yu Tsai Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Tue, 24 Nov 2015 11:13:13 +0800 Message-ID: References: <20151123124356.GW32142@lukather> Reply-To: wens-jdAy2FN1RRM@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <20151123124356.GW32142@lukather> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Maxime Ripard Cc: Josef Gajdusek , linux-sunxi , linux-clk , linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel , linux-arm-kernel , devicetree , gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, Mike Turquette , Hans De Goede , Stephen Boyd , Michael Turquette , Emilio Lopez , Russell King - ARM Linux , Eduardo Valentin , Zhang Rui , Chen-Yu Tsai , Kumar Gala , Ian Campbell , Mark Rutland , Pawel Moll , Rob Herring List-Id: linux-pm@vger.kernel.org Hi, On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard wrote: > Hi, > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: >> Add a node describing the Security ID memory to the >> Allwinner H3 .dtsi file. >> >> Signed-off-by: Josef Gajdusek >> --- >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi >> index 0faa38a..58de718 100644 >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >> @@ -359,6 +359,13 @@ >> #size-cells = <0>; >> }; >> >> + sid: eeprom@01c14000 { >> + compatible = "allwinner,sun4i-a10-sid"; >> + reg = <0x01c14000 0x400>; > > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > is it intentional? My H3 datasheet (v1.1) says its 1 kB wide. It'd be nice if Allwinner actually listed the "usable" E-fuse offsets and widths, instead of having us dig through the SDK code. Regards ChenYu From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sugar Wu Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Mon, 23 Nov 2015 19:24:40 -0800 (PST) Message-ID: <077cd975-1f91-40fe-ab05-2381e4fb6448@googlegroups.com> References: <20151123124356.GW32142@lukather> Reply-To: shugelinux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_7547_2088280689.1448335481093" Return-path: In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi Cc: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, atx-MwjtXicnQwU@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org ------=_Part_7547_2088280689.1448335481093 Content-Type: multipart/alternative; boundary="----=_Part_7548_1988214271.1448335481094" ------=_Part_7548_1988214271.1448335481094 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable I will give you the right widths as soon. =E5=9C=A8 2015=E5=B9=B411=E6=9C=8824=E6=97=A5=E6=98=9F=E6=9C=9F=E4=BA=8C UT= C+8=E4=B8=8A=E5=8D=8811:13:41=EF=BC=8CChen-Yu Tsai=E5=86=99=E9=81=93=EF=BC= =9A > > Hi,=20 > > On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard=20 > > wrote:=20 > > Hi,=20 > >=20 > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:=20 > >> Add a node describing the Security ID memory to the=20 > >> Allwinner H3 .dtsi file.=20 > >>=20 > >> Signed-off-by: Josef Gajdusek >=20 > >> ---=20 > >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++=20 > >> 1 file changed, 7 insertions(+)=20 > >>=20 > >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi=20 > b/arch/arm/boot/dts/sun8i-h3.dtsi=20 > >> index 0faa38a..58de718 100644=20 > >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi=20 > >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi=20 > >> @@ -359,6 +359,13 @@=20 > >> #size-cells =3D <0>;=20 > >> };=20 > >>=20 > >> + sid: eeprom@01c14000 {=20 > >> + compatible =3D "allwinner,sun4i-a10-sid";=20 > >> + reg =3D <0x01c14000 0x400>;=20 > >=20 > > The datasheet says it's 256 bytes wide, while the size here is of 1kB,= =20 > > is it intentional?=20 > > My H3 datasheet (v1.1) says its 1 kB wide.=20 > > It'd be nice if Allwinner actually listed the "usable" E-fuse offsets=20 > and widths, instead of having us dig through the SDK code.=20 > > Regards=20 > ChenYu=20 > --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. ------=_Part_7548_1988214271.1448335481094 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
I will give you the right=C2=A0widths as soon.

=E5= =9C=A8 2015=E5=B9=B411=E6=9C=8824=E6=97=A5=E6=98=9F=E6=9C=9F=E4=BA=8C UTC+8= =E4=B8=8A=E5=8D=8811:13:41=EF=BC=8CChen-Yu Tsai=E5=86=99=E9=81=93=EF=BC=9A<= blockquote class=3D"gmail_quote" style=3D"margin: 0;margin-left: 0.8ex;bord= er-left: 1px #ccc solid;padding-left: 1ex;">Hi,

On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard
<maxime...@free-electrons.com> wrote:
> Hi,
>
> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
>> Add a node describing the Security ID memory to the
>> Allwinner H3 .dtsi file.
>>
>> Signed-off-by: Josef Gajdusek <a...-MwjtXicnQwU@public.gmane.org>
>> ---
>> =C2=A0arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++
>> =C2=A01 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/b= oot/dts/sun8i-h3.dtsi
>> index 0faa38a..58de718 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -359,6 +359,13 @@
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 #size-cells =3D <0>;
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 };
>>
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 sid: eeprom@01c140= 00 {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 compatible =3D "allwinner,sun4i-a10-sid";
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 reg =3D <0x01c14000 0x400>;
>
> The datasheet says it's 256 bytes wide, while the size here is= of 1kB,
> is it intentional?

My H3 datasheet (v1.1) says its 1 kB wide.

It'd be nice if Allwinner actually listed the "usable" E-= fuse offsets
and widths, instead of having us dig through the SDK code.

Regards
ChenYu

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------=_Part_7548_1988214271.1448335481094-- ------=_Part_7547_2088280689.1448335481093-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Tue, 24 Nov 2015 07:38:30 +0100 Message-ID: <20151124063830.GC32142@lukather> References: <20151123124356.GW32142@lukather> <077cd975-1f91-40fe-ab05-2381e4fb6448@googlegroups.com> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="UIrAl4r1g2eOkvhC" Return-path: Content-Disposition: inline In-Reply-To: <077cd975-1f91-40fe-ab05-2381e4fb6448-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Sugar Wu Cc: linux-sunxi , atx-MwjtXicnQwU@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org --UIrAl4r1g2eOkvhC Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Mon, Nov 23, 2015 at 07:24:40PM -0800, Sugar Wu wrote: > I will give you the right widths as soon. Great, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --UIrAl4r1g2eOkvhC-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sugar Wu Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Mon, 23 Nov 2015 22:51:15 -0800 (PST) Message-ID: References: <20151123124356.GW32142@lukather> Reply-To: shugelinux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_7799_1307141804.1448347875675" Return-path: In-Reply-To: <20151123124356.GW32142@lukather> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi Cc: atx-MwjtXicnQwU@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org ------=_Part_7799_1307141804.1448347875675 Content-Type: multipart/alternative; boundary="----=_Part_7800_1893462329.1448347875675" ------=_Part_7800_1893462329.1448347875675 Content-Type: text/plain; charset=UTF-8 On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: > > Hi, > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > > Add a node describing the Security ID memory to the > > Allwinner H3 .dtsi file. > > > > Signed-off-by: Josef Gajdusek > > > --- > > arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi > b/arch/arm/boot/dts/sun8i-h3.dtsi > > index 0faa38a..58de718 100644 > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > > @@ -359,6 +359,13 @@ > > #size-cells = <0>; > > }; > > > > + sid: eeprom@01c14000 { > > + compatible = "allwinner,sun4i-a10-sid"; > > + reg = <0x01c14000 0x400>; > > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > is it intentional? SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space. H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. > > Thanks, > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. ------=_Part_7800_1893462329.1448347875675 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable

On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wro= te:
Hi,

On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
> Add a node describing the Security ID memory to the
> Allwinner H3 .dtsi file.
>=20
> Signed-off-by: Josef Gajdusek <a...-MwjtXicnQwU@public.gmane.org>
> ---
> =C2=A0arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++
> =C2=A01 file changed, 7 insertions(+)
>=20
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/= dts/sun8i-h3.dtsi
> index 0faa38a..58de718 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -359,6 +359,13 @@
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0#size-cells =3D <0>;
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0};
> =C2=A0
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0sid: eeprom@01c14000 {
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0compatible =3D "allwinner,sun4i-a10-sid";
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0reg =3D <0x01c14000 0x400>;

The datasheet says it's 256 bytes wide, while the size here is of 1= kB,
is it intentional?
SID memory map is 0x01c14000 ~ 0x0= 1c143FF, include 2048bits efuse space.
H3 efuse space is SID_SRAM= , its range is =C2=A00x01c14200 ~ +0x100.
=C2=A0
Thanks,
Maxime

--=20
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.c= om

--
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------=_Part_7800_1893462329.1448347875675-- ------=_Part_7799_1307141804.1448347875675-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Tue, 24 Nov 2015 08:26:13 +0100 Message-ID: <20151124072613.GF32142@lukather> References: <20151123124356.GW32142@lukather> <20151124063808.GB32142@lukather> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="h6w+13shfCQ8v2Yw" Return-path: Content-Disposition: inline In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Chen-Yu Tsai Cc: Josef Gajdusek , linux-sunxi , linux-clk , linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel , linux-arm-kernel , devicetree , gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, Mike Turquette , Hans De Goede , Stephen Boyd , Michael Turquette , Emilio Lopez , Russell King - ARM Linux , Eduardo Valentin , Zhang Rui , Kumar Gala , Ian Campbell , Mark Rutland , Pawel Moll , Rob Herring List-Id: linux-pm@vger.kernel.org --h6w+13shfCQ8v2Yw Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Tue, Nov 24, 2015 at 02:42:26PM +0800, Chen-Yu Tsai wrote: > On Tue, Nov 24, 2015 at 2:38 PM, Maxime Ripard > wrote: > > On Tue, Nov 24, 2015 at 11:13:13AM +0800, Chen-Yu Tsai wrote: > >> Hi, > >> > >> On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard > >> wrote: > >> > Hi, > >> > > >> > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > >> >> Add a node describing the Security ID memory to the > >> >> Allwinner H3 .dtsi file. > >> >> > >> >> Signed-off-by: Josef Gajdusek > >> >> --- > >> >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > >> >> 1 file changed, 7 insertions(+) > >> >> > >> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > >> >> index 0faa38a..58de718 100644 > >> >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi > >> >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > >> >> @@ -359,6 +359,13 @@ > >> >> #size-cells = <0>; > >> >> }; > >> >> > >> >> + sid: eeprom@01c14000 { > >> >> + compatible = "allwinner,sun4i-a10-sid"; > >> >> + reg = <0x01c14000 0x400>; > >> > > >> > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > >> > is it intentional? > >> > >> My H3 datasheet (v1.1) says its 1 kB wide. > > > > Is it? in the Security ID section, it is said to be 2kb == 256B wide. > > Right. I was looking at the memory map. Maybe it's sparsely mapped? > I guess we'll know soon. If it is just like the A20, I think there's a few registers at the end to control the writes (that we don't use). Which means that the size of the fuses is smaller than the size of the mapped area (which also measn that our driver is broken making that assumption). Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --h6w+13shfCQ8v2Yw-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Tue, 24 Nov 2015 10:32:02 +0100 Message-ID: <20151124093202.GL32142@lukather> References: <20151123124356.GW32142@lukather> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="9RXjJcDGNuBviZqz" Return-path: Content-Disposition: inline In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Sugar Wu Cc: linux-sunxi , atx-MwjtXicnQwU@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org --9RXjJcDGNuBviZqz Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Mon, Nov 23, 2015 at 10:51:15PM -0800, Sugar Wu wrote: > On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: > > > > Hi, > > > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > > > Add a node describing the Security ID memory to the > > > Allwinner H3 .dtsi file. > > > > > > Signed-off-by: Josef Gajdusek > > > > --- > > > arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > > > 1 file changed, 7 insertions(+) > > > > > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi > > b/arch/arm/boot/dts/sun8i-h3.dtsi > > > index 0faa38a..58de718 100644 > > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > > > @@ -359,6 +359,13 @@ > > > #size-cells = <0>; > > > }; > > > > > > + sid: eeprom@01c14000 { > > > + compatible = "allwinner,sun4i-a10-sid"; > > > + reg = <0x01c14000 0x400>; > > > > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > > is it intentional? > > SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space. > H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. Interesting, what is below the 0x200 registers? Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --9RXjJcDGNuBviZqz-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shuge Subject: Re: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Wed, 25 Nov 2015 09:22:56 +0800 Message-ID: <56550D70.6060109@gmail.com> References: <20151123124356.GW32142@lukather> <20151124093202.GL32142@lukather> Reply-To: shugelinux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <20151124093202.GL32142@lukather> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Maxime Ripard Cc: linux-sunxi , atx-MwjtXicnQwU@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org On Monday, November 23, 2015 at 17:32 UTC+8, Maxime Ripard wrote: > On Mon, Nov 23, 2015 at 10:51:15PM -0800, Sugar Wu wrote: >> On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: >>> >>> Hi, >>> >>> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: >>>> Add a node describing the Security ID memory to the >>>> Allwinner H3 .dtsi file. >>>> >>>> Signed-off-by: Josef Gajdusek > >>>> --- >>>> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ >>>> 1 file changed, 7 insertions(+) >>>> >>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi >>> b/arch/arm/boot/dts/sun8i-h3.dtsi >>>> index 0faa38a..58de718 100644 >>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi >>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >>>> @@ -359,6 +359,13 @@ >>>> #size-cells = <0>; >>>> }; >>>> >>>> + sid: eeprom@01c14000 { >>>> + compatible = "allwinner,sun4i-a10-sid"; >>>> + reg = <0x01c14000 0x400>; >>> >>> The datasheet says it's 256 bytes wide, while the size here is of 1kB, >>> is it intentional? >> >> SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space. >> H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. > > Interesting, what is below the 0x200 registers? > Some control register about SID. offset: 0x40 SID Program/Read Control Register offset: 0x50 SID Program Key Value Register offset: 0x60 SID Read Key Value Register offset: 0x70 \ offset: 0x80 SJTAG Attribute 0 Register offset: 0x84 SJTAG Attribute 1 Register offset: 0x88 SJTAG Select Register offset: 0x90 SID Program Ctrol register for burned timing > > Thanks! > Maxime > From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Josef Gajdusek" Subject: Re: Re: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor Date: Wed, 25 Nov 2015 11:02:34 +0000 Message-ID: <0edf1031924124377647dfb0f62ec6c8@rainloop.atalax.net> References: <20151124084342.GJ32142@lukather> Reply-To: atx-MwjtXicnQwU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: <20151124084342.GJ32142@lukather> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org November 24 2015 9:43 AM, "Maxime Ripard" wrote: > On Mon, Nov 23, 2015 at 09:02:50AM +0100, Josef Gajdusek wrote: > >> This patch adds support for the Sunxi thermal sensor on the Allwinner H3. > > You can drop the sunxi here. > >> Should be easily extendable for the A33/A83T/... as they have similar but >> not completely identical sensors. >> >> Signed-off-by: Josef Gajdusek >> --- >> drivers/thermal/Kconfig | 7 + >> drivers/thermal/Makefile | 1 + >> drivers/thermal/sun8i_ths.c | 365 ++++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 373 insertions(+) >> create mode 100644 drivers/thermal/sun8i_ths.c >> >> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig >> index c463c89..2b41147 100644 >> --- a/drivers/thermal/Kconfig >> +++ b/drivers/thermal/Kconfig >> @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL >> Thermal reporting device will provide temperature reading, >> programmable trip points and other information. >> >> +config SUN8I_THS >> + tristate "sun8i THS driver" >> + depends on MACH_SUN8I >> + depends on OF >> + help >> + Enable this to support thermal reporting on some newer Allwinner SoCs. >> + >> menu "Texas Instruments thermal drivers" >> depends on ARCH_HAS_BANDGAP || COMPILE_TEST >> source "drivers/thermal/ti-soc-thermal/Kconfig" >> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile >> index cfae6a6..227e1a1 100644 >> --- a/drivers/thermal/Makefile >> +++ b/drivers/thermal/Makefile >> @@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o >> obj-$(CONFIG_ST_THERMAL) += st/ >> obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o >> obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o >> +obj-$(CONFIG_SUN8I_THS) += sun8i_ths.o >> diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c >> new file mode 100644 >> index 0000000..2c976ac >> --- /dev/null >> +++ b/drivers/thermal/sun8i_ths.c >> @@ -0,0 +1,365 @@ >> +/* >> + * Sunxi THS driver > > sun8i Thermal Sensor Driver > >> + * Copyright (C) 2015 Josef Gajdusek >> + * >> + * This software is licensed under the terms of the GNU General Public >> + * License version 2, as published by the Free Software Foundation, and >> + * may be copied, distributed, and modified under those terms. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + */ >> + >> +#include >> +#include > > Are you using this header? > >> +#include >> +#include >> +#include > > You probably don't need this one too. > >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#define THS_H3_CTRL0 0x00 >> +#define THS_H3_CTRL1 0x04 >> +#define THS_H3_CDAT 0x14 >> +#define THS_H3_CTRL2 0x40 >> +#define THS_H3_INT_CTRL 0x44 >> +#define THS_H3_STAT 0x48 >> +#define THS_H3_ALARM_CTRL 0x50 >> +#define THS_H3_SHUTDOWN_CTRL 0x60 >> +#define THS_H3_FILTER 0x70 >> +#define THS_H3_CDATA 0x74 >> +#define THS_H3_DATA 0x80 >> + >> +#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS 0 >> +#define THS_H3_CTRL0_SENSOR_ACQ0(x) \ >> + ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS) >> +#define THS_H3_CTRL1_ADC_CALI_EN_OFFS 17 >> +#define THS_H3_CTRL1_ADC_CALI_EN \ >> + BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS) >> +#define THS_H3_CTRL1_OP_BIAS_OFFS 20 >> +#define THS_H3_CTRL1_OP_BIAS(x) \ >> + ((x) << THS_H3_CTRL1_OP_BIAS_OFFS) >> +#define THS_H3_CTRL2_SENSE_EN_OFFS 0 >> +#define THS_H3_CTRL2_SENSE_EN \ >> + BIT(THS_H3_CTRL2_SENSE_EN_OFFS) >> +#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS 16 >> +#define THS_H3_CTRL2_SENSOR_ACQ1(x) \ >> + ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS) >> + >> +#define THS_H3_INT_CTRL_ALARM_INT_EN_OFFS 0 >> +#define THS_H3_INT_CTRL_ALARM_INT_EN \ >> + BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS) >> +#define THS_H3_INT_CTRL_SHUT_INT_EN_OFFS 4 >> +#define THS_H3_INT_CTRL_SHUT_INT_EN \ >> + BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS) >> +#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS 8 >> +#define THS_H3_INT_CTRL_DATA_IRQ_EN \ >> + BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS) >> +#define THS_H3_INT_CTRL_THERMAL_PER_OFFS 12 >> +#define THS_H3_INT_CTRL_THERMAL_PER(x) \ >> + ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS) >> + >> +#define THS_H3_STAT_ALARM_INT_STS_OFFS 0 >> +#define THS_H3_STAT_ALARM_INT_STS \ >> + BIT(THS_H3_STAT_ALARM_INT_STS_OFFS) >> +#define THS_H3_STAT_SHUT_INT_STS_OFFS 4 >> +#define THS_H3_STAT_SHUT_INT_STS \ >> + BIT(THS_H3_STAT_SHUT_INT_STS_OFFS) >> +#define THS_H3_STAT_DATA_IRQ_STS_OFFS 8 >> +#define THS_H3_STAT_DATA_IRQ_STS \ >> + BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS) >> +#define THS_H3_STAT_ALARM_OFF_STS_OFFS 12 >> +#define THS_H3_STAT_ALARM_OFF_STS \ >> + BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS) >> + >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS 0 >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST(x) \ >> + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS) >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS 16 >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT(x) \ >> + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS) >> + >> +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS 16 >> +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT(x) \ >> + ((x) << THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS) >> + >> +#define THS_H3_FILTER_TYPE_OFFS 0 >> +#define THS_H3_FILTER_TYPE(x) \ >> + ((x) << THS_H3_FILTER_TYPE_OFFS) >> +#define THS_H3_FILTER_EN_OFFS 2 >> +#define THS_H3_FILTER_EN \ >> + BIT(THS_H3_FILTER_EN_OFFS) > > Are you using these offsets anywhere? >> + >> +#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0xff >> +#define THS_H3_INT_CTRL_THERMAL_PER_VALUE 0x79 >> +#define THS_H3_FILTER_TYPE_VALUE 0x2 >> +#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f >> + >> +struct sun8i_ths_data { >> + struct sun8i_ths_type *type; >> + struct reset_control *reset; >> + struct clk *clk; >> + struct clk *busclk; >> + void __iomem *regs; >> + struct nvmem_cell *calcell; >> + struct platform_device *pdev; >> + struct thermal_zone_device *tzd; >> +}; >> + >> +struct sun8i_ths_type { >> + int (*init)(struct platform_device *, struct sun8i_ths_data *); >> + int (*get_temp)(struct sun8i_ths_data *, int *out); >> + void (*irq)(struct sun8i_ths_data *); >> + void (*deinit)(struct sun8i_ths_data *); >> +}; > > AFAIK, you never got back on why it was actually needed, instead of > directly calling these functions. It is preparation for supporting the other SoCs with THS as they have slightly different register layouts and thus cannot be controlled by the same code. >> +/* Formula and parameters from the Allwinner 3.4 kernel */ >> +static int sun8i_ths_reg_to_temperature(s32 reg, int divisor, int constant) >> +{ >> + return constant - (reg * 1000000) / divisor; >> +} >> + >> +static int sun8i_ths_get_temp(void *_data, int *out) >> +{ >> + struct sun8i_ths_data *data = _data; >> + >> + return data->type->get_temp(data, out); >> +} >> + >> +static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data) >> +{ >> + struct sun8i_ths_data *data = _data; >> + >> + data->type->irq(data); >> + thermal_zone_device_update(data->tzd); >> + >> + return IRQ_HANDLED; >> +} >> + >> +static int sun8i_ths_h3_init(struct platform_device *pdev, >> + struct sun8i_ths_data *data) >> +{ >> + int ret; >> + size_t callen; >> + s32 *caldata; >> + >> + data->busclk = devm_clk_get(&pdev->dev, "ahb"); >> + if (IS_ERR(data->busclk)) { >> + ret = PTR_ERR(data->busclk); >> + dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret); >> + return ret; >> + } >> + >> + data->clk = devm_clk_get(&pdev->dev, "ths"); >> + if (IS_ERR(data->clk)) { >> + ret = PTR_ERR(data->clk); >> + dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret); >> + return ret; >> + } >> + >> + data->reset = devm_reset_control_get(&pdev->dev, "ahb"); >> + if (IS_ERR(data->reset)) { >> + ret = PTR_ERR(data->reset); >> + dev_err(&pdev->dev, "failed to get reset: %d\n", ret); >> + return ret; >> + } >> + >> + if (data->calcell) { >> + caldata = nvmem_cell_read(data->calcell, &callen); >> + if (IS_ERR(caldata)) >> + return PTR_ERR(caldata); >> + writel(be32_to_cpu(*caldata), data->regs + THS_H3_CDATA); >> + kfree(caldata); >> + } >> + >> + ret = clk_prepare_enable(data->busclk); >> + if (ret) { >> + dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret); >> + return ret; >> + } >> + >> + ret = clk_prepare_enable(data->clk); >> + if (ret) { >> + dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret); >> + goto err_disable_bus; >> + } >> + >> + ret = reset_control_deassert(data->reset); >> + if (ret) { >> + dev_err(&pdev->dev, "reset deassert failed: %d\n", ret); >> + goto err_disable_ths; >> + } >> + >> + /* The final sample period is calculated as follows: >> + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) >> + * >> + * This results to about 1Hz with these settings. >> + */ >> + ret = clk_set_rate(data->clk, 4000000); > > I don't follow you here. You have a complicated math function, that > has many input variables, and then, you just set the clock rate to a > constant? How should this be handled then? I guess the sampling rate could be set in the device tree and then the values calculated, but none of the other thermal drivers seem to have configurable sample rate. >> + if (ret) >> + goto err_disable_ths; > > A new line here please > >> + writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE), >> + data->regs + THS_H3_CTRL0); >> + writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) | >> + THS_H3_INT_CTRL_DATA_IRQ_EN, >> + data->regs + THS_H3_INT_CTRL); >> + writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE), >> + data->regs + THS_H3_FILTER); >> + writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) | >> + THS_H3_CTRL2_SENSE_EN, >> + data->regs + THS_H3_CTRL2); > > And here too. > >> + return 0; >> + >> +err_disable_ths: >> + clk_disable_unprepare(data->clk); >> +err_disable_bus: >> + clk_disable_unprepare(data->busclk); >> + >> + return ret; >> +} >> + >> +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *out) >> +{ >> + int val = readl(data->regs + THS_H3_DATA); >> + *out = sun8i_ths_reg_to_temperature(val, 8253, 217000); >> + return 0; > > Can't you just return the value directly? I did that in the v1, clabbe.montjoie suggested to use temp variable to avoid column wrap. >> +} >> + >> +static void sun8i_ths_h3_irq(struct sun8i_ths_data *data) >> +{ >> + writel(THS_H3_STAT_DATA_IRQ_STS | >> + THS_H3_STAT_ALARM_INT_STS | >> + THS_H3_STAT_ALARM_OFF_STS | >> + THS_H3_STAT_SHUT_INT_STS, >> + data->regs + THS_H3_STAT); > > So you're always clearing all the interrupts? Shouldn't you just clear > only the interrupt you received? > >> +} >> + >> +static void sun8i_ths_h3_deinit(struct sun8i_ths_data *data) >> +{ >> + reset_control_assert(data->reset); >> + clk_disable_unprepare(data->clk); >> + clk_disable_unprepare(data->busclk); >> +} >> + >> +static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = { >> + .get_temp = sun8i_ths_get_temp, >> +}; >> + >> +static const struct sun8i_ths_type sun8i_ths_device_h3 = { >> + .init = sun8i_ths_h3_init, >> + .get_temp = sun8i_ths_h3_get_temp, >> + .irq = sun8i_ths_h3_irq, >> + .deinit = sun8i_ths_h3_deinit, >> +}; >> + >> +static const struct of_device_id sun8i_ths_id_table[] = { >> + { >> + .compatible = "allwinner,sun8i-h3-ths", >> + .data = &sun8i_ths_device_h3, >> + }, >> + { >> + /* sentinel */ >> + }, >> +}; >> +MODULE_DEVICE_TABLE(of, sun8i_ths_id_table); >> + >> +static int sun8i_ths_probe(struct platform_device *pdev) >> +{ >> + struct device_node *np = pdev->dev.of_node; >> + const struct of_device_id *match; >> + struct sun8i_ths_data *data; >> + struct resource *res; >> + int ret; >> + int irq; >> + >> + match = of_match_node(sun8i_ths_id_table, np); > > If you *really* need to (but I still don't really see why), you can > use of_device_get_match_data here. > >> + >> + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); >> + if (!data) >> + return -ENOMEM; >> + >> + data->type = (struct sun8i_ths_type *)match->data; >> + data->pdev = pdev; >> + >> + data->calcell = devm_nvmem_cell_get(&pdev->dev, "calibration"); >> + if (IS_ERR(data->calcell)) { >> + if (PTR_ERR(data->calcell) == -EPROBE_DEFER) >> + return PTR_ERR(data->calcell); > > New line > >> + data->calcell = NULL; /* No calibration register */ > > s/register/data/ ? > >> + } >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + data->regs = devm_ioremap_resource(&pdev->dev, res); >> + if (IS_ERR(data->regs)) { >> + ret = PTR_ERR(data->regs); >> + dev_err(&pdev->dev, >> + "failed to ioremap THS registers: %d\n", ret); >> + return ret; >> + } >> + >> + irq = platform_get_irq(pdev, 0); >> + if (irq < 0) { >> + dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); >> + return irq; >> + } >> + >> + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, >> + sun8i_ths_irq_thread, IRQF_ONESHOT, >> + dev_name(&pdev->dev), data); > > Why a threaded irq? I thought threaded IRQs are preferred? Other thermal drivers use them too. I am also not really sure thermal_zone_device_update() can even be called in interrupt context. >> + if (ret) >> + return ret; >> + >> + ret = data->type->init(pdev, data); >> + if (ret) >> + return ret; >> + >> + data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, >> + &sun8i_ths_thermal_ops); >> + if (IS_ERR(data->tzd)) { >> + ret = PTR_ERR(data->tzd); >> + dev_err(&pdev->dev, "failed to register thermal zone: %d\n", >> + ret); >> + goto err_deinit; >> + } >> + >> + platform_set_drvdata(pdev, data); >> + return 0; >> + >> +err_deinit: >> + data->type->deinit(data); >> + return ret; >> +} >> + >> +static int sun8i_ths_remove(struct platform_device *pdev) >> +{ >> + struct sun8i_ths_data *data = platform_get_drvdata(pdev); >> + >> + thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); >> + data->type->deinit(data); >> + return 0; >> +} >> + >> +static struct platform_driver sun8i_ths_driver = { >> + .probe = sun8i_ths_probe, >> + .remove = sun8i_ths_remove, >> + .driver = { >> + .name = "sun8i_ths", >> + .of_match_table = sun8i_ths_id_table, >> + }, >> +}; >> + >> +module_platform_driver(sun8i_ths_driver); >> + >> +MODULE_AUTHOR("Josef Gajdusek "); >> +MODULE_DESCRIPTION("Sunxi THS driver"); > > Please change the description here too to match the header. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to > linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org > For more options, visit https://groups.google.com/d/optout. Josef Gajdusek From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: Re: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor Date: Mon, 30 Nov 2015 20:58:23 +0100 Message-ID: <20151130195823.GE3664@lukather> References: <20151124084342.GJ32142@lukather> <0edf1031924124377647dfb0f62ec6c8@rainloop.atalax.net> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="KlAEzMkarCnErv5Q" Return-path: Content-Disposition: inline In-Reply-To: <0edf1031924124377647dfb0f62ec6c8-DwCxqXnXFIKSaDSPXN/tZNHuzzzSOjJt@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Josef Gajdusek Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org --KlAEzMkarCnErv5Q Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Wed, Nov 25, 2015 at 11:02:34AM +0000, Josef Gajdusek wrote: > >> +struct sun8i_ths_type { > >> + int (*init)(struct platform_device *, struct sun8i_ths_data *); > >> + int (*get_temp)(struct sun8i_ths_data *, int *out); > >> + void (*irq)(struct sun8i_ths_data *); > >> + void (*deinit)(struct sun8i_ths_data *); > >> +}; > > > > AFAIK, you never got back on why it was actually needed, instead of > > directly calling these functions. > > It is preparation for supporting the other SoCs with THS as they have > slightly different register layouts and thus cannot be controlled by the > same code. Do you have support and / or informations on what's going to be needed for these other SoCs yet? Which SoCs are we talking about? > >> + /* The final sample period is calculated as follows: > >> + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) > >> + * > >> + * This results to about 1Hz with these settings. > >> + */ > >> + ret = clk_set_rate(data->clk, 4000000); > > > > I don't follow you here. You have a complicated math function, that > > has many input variables, and then, you just set the clock rate to a > > constant? > > How should this be handled then? I guess the sampling rate could > be set in the device tree and then the values calculated, but none > of the other thermal drivers seem to have configurable sample rate. I don't know, I would have expected some actual computation, like a function taking the frequency as a parameter and returning the clock rate. At least that way we now what we're doing and which part might change and which will not. But you do not need to change the sample rate itself. > >> +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *out) > >> +{ > >> + int val = readl(data->regs + THS_H3_DATA); > >> + *out = sun8i_ths_reg_to_temperature(val, 8253, 217000); > >> + return 0; > > > > Can't you just return the value directly? > > I did that in the v1, clabbe.montjoie suggested to use temp variable to > avoid column wrap. I was talking about the out pointer. Can the value not be returned? > >> + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, > >> + sun8i_ths_irq_thread, IRQF_ONESHOT, > >> + dev_name(&pdev->dev), data); > > > > Why a threaded irq? > > I thought threaded IRQs are preferred? Other thermal drivers > use them too. It's close to pointless in this case. You're not doing much more than what the default handler will do anyway, and you avoid scheduling a thread doing so. And other thermal drivers use a regular interrupt handler too :) > I am also not really sure thermal_zone_device_update() can even be > called in interrupt context. I can't really tell on this one. Judging from a quick look, I can't see anything that could prevent it, and since others are using it, it seems doable. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --KlAEzMkarCnErv5Q-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node Date: Tue, 1 Dec 2015 09:41:17 +0100 Message-ID: <20151201084117.GB29263@lukather> References: <20151123124356.GW32142@lukather> <20151124093202.GL32142@lukather> <56550D70.6060109@gmail.com> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="PmA2V3Z32TCmWXqI" Return-path: Content-Disposition: inline In-Reply-To: <56550D70.6060109-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Shuge Cc: linux-sunxi , atx-MwjtXicnQwU@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gpatchesrdh-I1/eAgTnXDYAvxtiuMwx3w@public.gmane.org, mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org List-Id: linux-pm@vger.kernel.org --PmA2V3Z32TCmWXqI Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Hi, On Wed, Nov 25, 2015 at 09:22:56AM +0800, Shuge wrote: > On Monday, November 23, 2015 at 17:32 UTC+8, Maxime Ripard wrote: > > On Mon, Nov 23, 2015 at 10:51:15PM -0800, Sugar Wu wrote: > >> On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: > >>> > >>> Hi, > >>> > >>> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > >>>> Add a node describing the Security ID memory to the > >>>> Allwinner H3 .dtsi file. > >>>> > >>>> Signed-off-by: Josef Gajdusek > > >>>> --- > >>>> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > >>>> 1 file changed, 7 insertions(+) > >>>> > >>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi > >>> b/arch/arm/boot/dts/sun8i-h3.dtsi > >>>> index 0faa38a..58de718 100644 > >>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi > >>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > >>>> @@ -359,6 +359,13 @@ > >>>> #size-cells = <0>; > >>>> }; > >>>> > >>>> + sid: eeprom@01c14000 { > >>>> + compatible = "allwinner,sun4i-a10-sid"; > >>>> + reg = <0x01c14000 0x400>; > >>> > >>> The datasheet says it's 256 bytes wide, while the size here is of 1kB, > >>> is it intentional? > >> > >> SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space. > >> H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. > > > > Interesting, what is below the 0x200 registers? > > > Some control register about SID. > offset: 0x40 SID Program/Read Control Register > offset: 0x50 SID Program Key Value Register > offset: 0x60 SID Read Key Value Register > offset: 0x70 \ > offset: 0x80 SJTAG Attribute 0 Register > offset: 0x84 SJTAG Attribute 1 Register > offset: 0x88 SJTAG Select Register > offset: 0x90 SID Program Ctrol register for burned timing Thanks! I guess the layout changed a bit from the A10 and alikes then. Anyway, we should expose only to the nvmem framework the actual eeprom space, so from 0x200 to 0x300 from what you're saying (just like we should only expose the first 4 bytes in the A10 / A20) Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --PmA2V3Z32TCmWXqI-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: atx@atx.name (Josef Gajdusek) Date: Mon, 23 Nov 2015 09:02:48 +0100 Subject: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node In-Reply-To: References: Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Add a node describing the Security ID memory to the Allwinner H3 .dtsi file. Signed-off-by: Josef Gajdusek --- arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 0faa38a..58de718 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -359,6 +359,13 @@ #size-cells = <0>; }; + sid: eeprom at 01c14000 { + compatible = "allwinner,sun4i-a10-sid"; + reg = <0x01c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + usbphy: phy at 01c19400 { compatible = "allwinner,sun8i-h3-usb-phy"; reg = <0x01c19400 0x2c>, -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: atx@atx.name (Josef Gajdusek) Date: Mon, 23 Nov 2015 09:02:51 +0100 Subject: [PATCH v2 4/5] dt-bindings: document sun8i_ths In-Reply-To: References: Message-ID: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch adds the binding documentation for the sun8i_ths driver Signed-off-by: Josef Gajdusek --- .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt new file mode 100644 index 0000000..67056bf --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt @@ -0,0 +1,31 @@ +* sun8i THS + +Required properties: +- compatible : "allwinner,sun8i-h3-ths" +- reg : Address range of the thermal registers and location of the calibration + value +- resets : Must contain an entry for each entry in reset-names. + see ../reset/reset.txt for details +- reset-names : Must include the name "ahb" +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS + clock + +Optional properties: +- nvmem-cells : Must contain an entry for each entry in nvmem-cell-names +- nvmem-cell-names : Must contain "calibration" for the cell containing the + temperature calibration cell, if available + +Example: +ths: ths at 01c25000 { + #thermal-sensor-cells = <0>; + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x88>, <0x01c14234 0x4>; + interrupts = ; + resets = <&bus_rst 136>; + reset-names = "ahb"; + clocks = <&bus_gates 72>, <&ths_clk>; + clock-names = "ahb", "ths"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; +}; -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: atx@atx.name (Josef Gajdusek) Date: Mon, 23 Nov 2015 09:02:47 +0100 Subject: [PATCH v2 0/5] sunxi: THS support Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hello everyone, this is v2 of my THS patchset Changelog: * Some stylistic changes * devm_reset_control_get_optional -> devm_reset_control_get * Added the clk-h3-ths clock driver - Note: A23/A33/A83T do not have a separate clock, H3 seems to be the first (and only?) SoC with it - Because of this, I moved the clock init code to the H3-specific init function. * Use the nvmem cell abstraction instead of accessing the configuration memory directly * Use the IRQ line (and fixed incorrect interrupt number in the DTS) * Renamed to sun8i_ths Ad the "magical constants": what I meant is that altough the datasheet explains what they are, it does not explain how to pick their values. "ADC" and "Sensor" "acquire time" are also not exactly the most helpful descriptions. Anyway, I changed the values such as the final sampling rate is about 1Hz. Josef Gajdusek (5): ARM: dts: sun8i: Add SID node clk: sunxi: Add driver for the H3 THS clock thermal: Add a driver for the Allwinner THS sensor dt-bindings: document sun8i_ths ARM: dts: sun8i: Add THS node to the H3 .dtsi Documentation/devicetree/bindings/clock/sunxi.txt | 1 + .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++ arch/arm/boot/dts/sun8i-h3.dtsi | 40 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-h3-ths.c | 98 ++++++ drivers/thermal/Kconfig | 7 + drivers/thermal/Makefile | 1 + drivers/thermal/sun8i_ths.c | 365 +++++++++++++++++++++ 8 files changed, 544 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt create mode 100644 drivers/clk/sunxi/clk-h3-ths.c create mode 100644 drivers/thermal/sun8i_ths.c -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: atx@atx.name (Josef Gajdusek) Date: Mon, 23 Nov 2015 09:02:49 +0100 Subject: [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock In-Reply-To: References: Message-ID: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch adds a driver for the THS clock which is present on the Allwinner H3. Signed-off-by: Josef Gajdusek --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-h3-ths.c | 98 +++++++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/clk/sunxi/clk-h3-ths.c diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 23e7bce..6d63b35 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -73,6 +73,7 @@ Required properties: "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 + "allwinner,sun8i-h3-ths-clk" - for THS on H3 Required properties for all clocks: - reg : shall be the control register address for the clock. diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index f520af6..1bf8e1c 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -8,6 +8,7 @@ obj-y += clk-a10-hosc.o obj-y += clk-a10-mod1.o obj-y += clk-a10-pll2.o obj-y += clk-a20-gmac.o +obj-y += clk-h3-ths.o obj-y += clk-mod0.o obj-y += clk-simple-gates.o obj-y += clk-sun8i-bus-gates.o diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk-h3-ths.c new file mode 100644 index 0000000..663afc0 --- /dev/null +++ b/drivers/clk/sunxi/clk-h3-ths.c @@ -0,0 +1,98 @@ +/* + * Sunxi THS clock driver + * + * Copyright (C) 2015 Josef Gajdusek + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#define SUN8I_H3_THS_CLK_ENABLE 31 +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0 +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2 + +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock); + +static const struct clk_div_table sun8i_h3_ths_clk_table[] __initconst = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 6 }, + { } /* sentinel */ +}; + +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) +{ + struct clk *clk; + struct clk_gate *gate; + struct clk_divider *div; + const char *parent; + const char *clk_name = node->name; + void __iomem *reg; + int err; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + + if (IS_ERR(reg)) + return; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto err_unmap; + + div = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!div) + goto err_gate_free; + + of_property_read_string(node, "clock-output-names", &clk_name); + parent = of_clk_get_parent_name(node, 0); + + gate->reg = reg; + gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE; + gate->lock = &sun8i_h3_ths_clk_lock; + + div->reg = reg; + div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT; + div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH; + div->table = sun8i_h3_ths_clk_table; + div->lock = &sun8i_h3_ths_clk_lock; + + clk = clk_register_composite(NULL, clk_name, &parent, 1, + NULL, NULL, + &div->hw, &clk_divider_ops, + &gate->hw, &clk_gate_ops, + CLK_SET_RATE_PARENT); + + if (IS_ERR(clk)) + goto err_div_free; + + err = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (err) + goto err_unregister_clk; + + return; + +err_unregister_clk: + clk_unregister(clk); +err_gate_free: + kfree(gate); +err_div_free: + kfree(div); +err_unmap: + iounmap(reg); +} + +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk", + sun8i_h3_ths_clk_setup); -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: atx@atx.name (Josef Gajdusek) Date: Mon, 23 Nov 2015 09:02:50 +0100 Subject: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor In-Reply-To: References: Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch adds support for the Sunxi thermal sensor on the Allwinner H3. Should be easily extendable for the A33/A83T/... as they have similar but not completely identical sensors. Signed-off-by: Josef Gajdusek --- drivers/thermal/Kconfig | 7 + drivers/thermal/Makefile | 1 + drivers/thermal/sun8i_ths.c | 365 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 373 insertions(+) create mode 100644 drivers/thermal/sun8i_ths.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index c463c89..2b41147 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config SUN8I_THS + tristate "sun8i THS driver" + depends on MACH_SUN8I + depends on OF + help + Enable this to support thermal reporting on some newer Allwinner SoCs. + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index cfae6a6..227e1a1 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_SUN8I_THS) += sun8i_ths.o diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c new file mode 100644 index 0000000..2c976ac --- /dev/null +++ b/drivers/thermal/sun8i_ths.c @@ -0,0 +1,365 @@ +/* + * Sunxi THS driver + * + * Copyright (C) 2015 Josef Gajdusek + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define THS_H3_CTRL0 0x00 +#define THS_H3_CTRL1 0x04 +#define THS_H3_CDAT 0x14 +#define THS_H3_CTRL2 0x40 +#define THS_H3_INT_CTRL 0x44 +#define THS_H3_STAT 0x48 +#define THS_H3_ALARM_CTRL 0x50 +#define THS_H3_SHUTDOWN_CTRL 0x60 +#define THS_H3_FILTER 0x70 +#define THS_H3_CDATA 0x74 +#define THS_H3_DATA 0x80 + +#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS 0 +#define THS_H3_CTRL0_SENSOR_ACQ0(x) \ + ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS) +#define THS_H3_CTRL1_ADC_CALI_EN_OFFS 17 +#define THS_H3_CTRL1_ADC_CALI_EN \ + BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS) +#define THS_H3_CTRL1_OP_BIAS_OFFS 20 +#define THS_H3_CTRL1_OP_BIAS(x) \ + ((x) << THS_H3_CTRL1_OP_BIAS_OFFS) +#define THS_H3_CTRL2_SENSE_EN_OFFS 0 +#define THS_H3_CTRL2_SENSE_EN \ + BIT(THS_H3_CTRL2_SENSE_EN_OFFS) +#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS 16 +#define THS_H3_CTRL2_SENSOR_ACQ1(x) \ + ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS) + +#define THS_H3_INT_CTRL_ALARM_INT_EN_OFFS 0 +#define THS_H3_INT_CTRL_ALARM_INT_EN \ + BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS) +#define THS_H3_INT_CTRL_SHUT_INT_EN_OFFS 4 +#define THS_H3_INT_CTRL_SHUT_INT_EN \ + BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS) +#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS 8 +#define THS_H3_INT_CTRL_DATA_IRQ_EN \ + BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS) +#define THS_H3_INT_CTRL_THERMAL_PER_OFFS 12 +#define THS_H3_INT_CTRL_THERMAL_PER(x) \ + ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS) + +#define THS_H3_STAT_ALARM_INT_STS_OFFS 0 +#define THS_H3_STAT_ALARM_INT_STS \ + BIT(THS_H3_STAT_ALARM_INT_STS_OFFS) +#define THS_H3_STAT_SHUT_INT_STS_OFFS 4 +#define THS_H3_STAT_SHUT_INT_STS \ + BIT(THS_H3_STAT_SHUT_INT_STS_OFFS) +#define THS_H3_STAT_DATA_IRQ_STS_OFFS 8 +#define THS_H3_STAT_DATA_IRQ_STS \ + BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS) +#define THS_H3_STAT_ALARM_OFF_STS_OFFS 12 +#define THS_H3_STAT_ALARM_OFF_STS \ + BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS) + +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS 0 +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST(x) \ + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS) +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS 16 +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT(x) \ + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS) + +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS 16 +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT(x) \ + ((x) << THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS) + +#define THS_H3_FILTER_TYPE_OFFS 0 +#define THS_H3_FILTER_TYPE(x) \ + ((x) << THS_H3_FILTER_TYPE_OFFS) +#define THS_H3_FILTER_EN_OFFS 2 +#define THS_H3_FILTER_EN \ + BIT(THS_H3_FILTER_EN_OFFS) + +#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0xff +#define THS_H3_INT_CTRL_THERMAL_PER_VALUE 0x79 +#define THS_H3_FILTER_TYPE_VALUE 0x2 +#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f + +struct sun8i_ths_data { + struct sun8i_ths_type *type; + struct reset_control *reset; + struct clk *clk; + struct clk *busclk; + void __iomem *regs; + struct nvmem_cell *calcell; + struct platform_device *pdev; + struct thermal_zone_device *tzd; +}; + +struct sun8i_ths_type { + int (*init)(struct platform_device *, struct sun8i_ths_data *); + int (*get_temp)(struct sun8i_ths_data *, int *out); + void (*irq)(struct sun8i_ths_data *); + void (*deinit)(struct sun8i_ths_data *); +}; + +/* Formula and parameters from the Allwinner 3.4 kernel */ +static int sun8i_ths_reg_to_temperature(s32 reg, int divisor, int constant) +{ + return constant - (reg * 1000000) / divisor; +} + +static int sun8i_ths_get_temp(void *_data, int *out) +{ + struct sun8i_ths_data *data = _data; + + return data->type->get_temp(data, out); +} + +static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data) +{ + struct sun8i_ths_data *data = _data; + + data->type->irq(data); + thermal_zone_device_update(data->tzd); + + return IRQ_HANDLED; +} + +static int sun8i_ths_h3_init(struct platform_device *pdev, + struct sun8i_ths_data *data) +{ + int ret; + size_t callen; + s32 *caldata; + + data->busclk = devm_clk_get(&pdev->dev, "ahb"); + if (IS_ERR(data->busclk)) { + ret = PTR_ERR(data->busclk); + dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret); + return ret; + } + + data->clk = devm_clk_get(&pdev->dev, "ths"); + if (IS_ERR(data->clk)) { + ret = PTR_ERR(data->clk); + dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret); + return ret; + } + + data->reset = devm_reset_control_get(&pdev->dev, "ahb"); + if (IS_ERR(data->reset)) { + ret = PTR_ERR(data->reset); + dev_err(&pdev->dev, "failed to get reset: %d\n", ret); + return ret; + } + + if (data->calcell) { + caldata = nvmem_cell_read(data->calcell, &callen); + if (IS_ERR(caldata)) + return PTR_ERR(caldata); + writel(be32_to_cpu(*caldata), data->regs + THS_H3_CDATA); + kfree(caldata); + } + + ret = clk_prepare_enable(data->busclk); + if (ret) { + dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(data->clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret); + goto err_disable_bus; + } + + ret = reset_control_deassert(data->reset); + if (ret) { + dev_err(&pdev->dev, "reset deassert failed: %d\n", ret); + goto err_disable_ths; + } + + /* The final sample period is calculated as follows: + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) + * + * This results to about 1Hz with these settings. + */ + ret = clk_set_rate(data->clk, 4000000); + if (ret) + goto err_disable_ths; + writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE), + data->regs + THS_H3_CTRL0); + writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) | + THS_H3_INT_CTRL_DATA_IRQ_EN, + data->regs + THS_H3_INT_CTRL); + writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE), + data->regs + THS_H3_FILTER); + writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) | + THS_H3_CTRL2_SENSE_EN, + data->regs + THS_H3_CTRL2); + return 0; + +err_disable_ths: + clk_disable_unprepare(data->clk); +err_disable_bus: + clk_disable_unprepare(data->busclk); + + return ret; +} + +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *out) +{ + int val = readl(data->regs + THS_H3_DATA); + *out = sun8i_ths_reg_to_temperature(val, 8253, 217000); + return 0; +} + +static void sun8i_ths_h3_irq(struct sun8i_ths_data *data) +{ + writel(THS_H3_STAT_DATA_IRQ_STS | + THS_H3_STAT_ALARM_INT_STS | + THS_H3_STAT_ALARM_OFF_STS | + THS_H3_STAT_SHUT_INT_STS, + data->regs + THS_H3_STAT); +} + +static void sun8i_ths_h3_deinit(struct sun8i_ths_data *data) +{ + reset_control_assert(data->reset); + clk_disable_unprepare(data->clk); + clk_disable_unprepare(data->busclk); +} + +static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = { + .get_temp = sun8i_ths_get_temp, +}; + +static const struct sun8i_ths_type sun8i_ths_device_h3 = { + .init = sun8i_ths_h3_init, + .get_temp = sun8i_ths_h3_get_temp, + .irq = sun8i_ths_h3_irq, + .deinit = sun8i_ths_h3_deinit, +}; + +static const struct of_device_id sun8i_ths_id_table[] = { + { + .compatible = "allwinner,sun8i-h3-ths", + .data = &sun8i_ths_device_h3, + }, + { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, sun8i_ths_id_table); + +static int sun8i_ths_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + struct sun8i_ths_data *data; + struct resource *res; + int ret; + int irq; + + match = of_match_node(sun8i_ths_id_table, np); + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->type = (struct sun8i_ths_type *)match->data; + data->pdev = pdev; + + data->calcell = devm_nvmem_cell_get(&pdev->dev, "calibration"); + if (IS_ERR(data->calcell)) { + if (PTR_ERR(data->calcell) == -EPROBE_DEFER) + return PTR_ERR(data->calcell); + data->calcell = NULL; /* No calibration register */ + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->regs)) { + ret = PTR_ERR(data->regs); + dev_err(&pdev->dev, + "failed to ioremap THS registers: %d\n", ret); + return ret; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); + return irq; + } + + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, + sun8i_ths_irq_thread, IRQF_ONESHOT, + dev_name(&pdev->dev), data); + if (ret) + return ret; + + ret = data->type->init(pdev, data); + if (ret) + return ret; + + data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, + &sun8i_ths_thermal_ops); + if (IS_ERR(data->tzd)) { + ret = PTR_ERR(data->tzd); + dev_err(&pdev->dev, "failed to register thermal zone: %d\n", + ret); + goto err_deinit; + } + + platform_set_drvdata(pdev, data); + return 0; + +err_deinit: + data->type->deinit(data); + return ret; +} + +static int sun8i_ths_remove(struct platform_device *pdev) +{ + struct sun8i_ths_data *data = platform_get_drvdata(pdev); + + thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); + data->type->deinit(data); + return 0; +} + +static struct platform_driver sun8i_ths_driver = { + .probe = sun8i_ths_probe, + .remove = sun8i_ths_remove, + .driver = { + .name = "sun8i_ths", + .of_match_table = sun8i_ths_id_table, + }, +}; + +module_platform_driver(sun8i_ths_driver); + +MODULE_AUTHOR("Josef Gajdusek "); +MODULE_DESCRIPTION("Sunxi THS driver"); +MODULE_LICENSE("GPL v2"); -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: atx@atx.name (Josef Gajdusek) Date: Mon, 23 Nov 2015 09:02:52 +0100 Subject: [PATCH v2 5/5] ARM: dts: sun8i: Add THS node to the H3 .dtsi In-Reply-To: References: Message-ID: <0fff612e26bf9cda9027a4175e16d25a0c2cc62c.1448263428.git.atx@atx.name> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch adds nodes for the THS driver and the THS clock to the Allwinner H3 .dtsi file. Signed-off-by: Josef Gajdusek --- arch/arm/boot/dts/sun8i-h3.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 58de718..48500d4 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -77,6 +77,14 @@ }; }; + thermal-zones { + cpu_thermal: cpu_thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 0>; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , @@ -236,6 +244,14 @@ "ahb1_ephy", "ahb1_dbg"; }; + ths_clk: clk at 01c20074 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ths-clk"; + reg = <0x01c20074 0x4>; + clocks = <&osc24M>; + clock-output-names = "ths"; + }; + mmc0_clk: clk at 01c20088 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; @@ -364,6 +380,10 @@ reg = <0x01c14000 0x400>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: calib at 234 { + reg = <0x234 0x4>; + }; }; usbphy: phy at 01c19400 { @@ -529,6 +549,19 @@ interrupts = ; }; + ths: ths at 01c25000 { + #thermal-sensor-cells = <0>; + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x88>; + interrupts = ; + resets = <&bus_rst 104>; + reset-names = "ahb"; + clocks = <&bus_gates 72>, <&ths_clk>; + clock-names = "ahb", "ths"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + }; + uart0: serial at 01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- 2.4.10 From mboxrd@z Thu Jan 1 00:00:00 1970 From: wens@csie.org (Chen-Yu Tsai) Date: Mon, 23 Nov 2015 17:47:11 +0800 Subject: [PATCH v2 4/5] dt-bindings: document sun8i_ths In-Reply-To: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> References: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Nov 23, 2015 at 4:02 PM, Josef Gajdusek wrote: > This patch adds the binding documentation for the sun8i_ths driver > > Signed-off-by: Josef Gajdusek > --- > .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt > > diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > new file mode 100644 > index 0000000..67056bf > --- /dev/null > +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > @@ -0,0 +1,31 @@ > +* sun8i THS > + > +Required properties: > +- compatible : "allwinner,sun8i-h3-ths" > +- reg : Address range of the thermal registers and location of the calibration > + value You are now using nvmem for the calibration data. You don't need the second entry. > +- resets : Must contain an entry for each entry in reset-names. > + see ../reset/reset.txt for details > +- reset-names : Must include the name "ahb" > +- clocks : Must contain an entry for each entry in clock-names. > +- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS > + clock > + > +Optional properties: > +- nvmem-cells : Must contain an entry for each entry in nvmem-cell-names > +- nvmem-cell-names : Must contain "calibration" for the cell containing the > + temperature calibration cell, if available > + > +Example: > +ths: ths at 01c25000 { > + #thermal-sensor-cells = <0>; > + compatible = "allwinner,sun8i-h3-ths"; > + reg = <0x01c25000 0x88>, <0x01c14234 0x4>; Same here. ChenYu > + interrupts = ; > + resets = <&bus_rst 136>; > + reset-names = "ahb"; > + clocks = <&bus_gates 72>, <&ths_clk>; > + clock-names = "ahb", "ths"; > + nvmem-cells = <&ths_calibration>; > + nvmem-cell-names = "calibration"; > +}; > -- > 2.4.10 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: plaes@plaes.org (Priit Laes) Date: Mon, 23 Nov 2015 12:28:09 +0200 Subject: [linux-sunxi] [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock In-Reply-To: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> References: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> Message-ID: <1448274489.27496.1.camel@plaes.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, 2015-11-23 at 09:02 +0100, Josef Gajdusek wrote: > This patch adds a driver for the THS clock which is present on the > Allwinner H3. > > Signed-off-by: Josef Gajdusek > --- > ?Documentation/devicetree/bindings/clock/sunxi.txt |??1 + > ?drivers/clk/sunxi/Makefile????????????????????????|??1 + > ?drivers/clk/sunxi/clk-h3-ths.c????????????????????| 98 > +++++++++++++++++++++++ > ?3 files changed, 100 insertions(+) > ?create mode 100644 drivers/clk/sunxi/clk-h3-ths.c > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt > b/Documentation/devicetree/bindings/clock/sunxi.txt > index 23e7bce..6d63b35 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -73,6 +73,7 @@ Required properties: > ? "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 > ? "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets > on A80 > ? "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + > resets on A80 > + "allwinner,sun8i-h3-ths-clk" - for THS on H3 > ? > ?Required properties for all clocks: > ?- reg : shall be the control register address for the clock. > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index f520af6..1bf8e1c 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -8,6 +8,7 @@ obj-y += clk-a10-hosc.o > ?obj-y += clk-a10-mod1.o > ?obj-y += clk-a10-pll2.o > ?obj-y += clk-a20-gmac.o > +obj-y += clk-h3-ths.o > ?obj-y += clk-mod0.o > ?obj-y += clk-simple-gates.o > ?obj-y += clk-sun8i-bus-gates.o > diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk- > h3-ths.c > new file mode 100644 > index 0000000..663afc0 > --- /dev/null > +++ b/drivers/clk/sunxi/clk-h3-ths.c > @@ -0,0 +1,98 @@ > +/* > + * Sunxi THS clock driver This should be "Allwinner H3 THS clock driver" > + * > + * Copyright (C) 2015 Josef Gajdusek > + * > + * This software is licensed under the terms of the GNU General > Public > + * License version 2, as published by the Free Software Foundation, > and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > + > +#define SUN8I_H3_THS_CLK_ENABLE 31 > +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0 > +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2 > + > +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock); > + > +static const struct clk_div_table sun8i_h3_ths_clk_table[] > __initconst = { > + { .val = 0, .div = 1 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 6 }, > + { } /* sentinel */ > +}; > + > +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) > +{ > + struct clk *clk; > + struct clk_gate *gate; > + struct clk_divider *div; > + const char *parent; > + const char *clk_name = node->name; > + void __iomem *reg; > + int err; > + > + reg = of_io_request_and_map(node, 0, > of_node_full_name(node)); > + > + if (IS_ERR(reg)) > + return; > + > + gate = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!gate) > + goto err_unmap; > + > + div = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!div) > + goto err_gate_free; > + > + of_property_read_string(node, "clock-output-names", > &clk_name); > + parent = of_clk_get_parent_name(node, 0); > + > + gate->reg = reg; > + gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE; > + gate->lock = &sun8i_h3_ths_clk_lock; > + > + div->reg = reg; > + div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT; > + div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH; > + div->table = sun8i_h3_ths_clk_table; > + div->lock = &sun8i_h3_ths_clk_lock; > + > + clk = clk_register_composite(NULL, clk_name, &parent, 1, > + ?????NULL, NULL, > + ?????&div->hw, &clk_divider_ops, > + ?????&gate->hw, &clk_gate_ops, > + ?????CLK_SET_RATE_PARENT); > + > + if (IS_ERR(clk)) > + goto err_div_free; > + > + err = of_clk_add_provider(node, of_clk_src_simple_get, clk); > + if (err) > + goto err_unregister_clk; > + > + return; > + > +err_unregister_clk: > + clk_unregister(clk); > +err_gate_free: > + kfree(gate); > +err_div_free: > + kfree(div); > +err_unmap: > + iounmap(reg); > +} > + > +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk", > + ???????sun8i_h3_ths_clk_setup); > -- > 2.4.10 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Mon, 23 Nov 2015 13:38:37 +0100 Subject: [PATCH v2 4/5] dt-bindings: document sun8i_ths In-Reply-To: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> References: <20e229f191031b0b0bff96dee118d1f2d988d7b3.1448263428.git.atx@atx.name> Message-ID: <20151123123837.GV32142@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, On Mon, Nov 23, 2015 at 09:02:51AM +0100, Josef Gajdusek wrote: > This patch adds the binding documentation for the sun8i_ths driver > > Signed-off-by: Josef Gajdusek > --- > .../devicetree/bindings/thermal/sun8i-ths.txt | 31 ++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt > > diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > new file mode 100644 > index 0000000..67056bf > --- /dev/null > +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt > @@ -0,0 +1,31 @@ > +* sun8i THS > + > +Required properties: > +- compatible : "allwinner,sun8i-h3-ths" > +- reg : Address range of the thermal registers and location of the calibration > + value > +- resets : Must contain an entry for each entry in reset-names. > + see ../reset/reset.txt for details > +- reset-names : Must include the name "ahb" If you have a single reset line, you don't need reset-names. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Mon, 23 Nov 2015 13:43:56 +0100 Subject: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node In-Reply-To: References: Message-ID: <20151123124356.GW32142@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > Add a node describing the Security ID memory to the > Allwinner H3 .dtsi file. > > Signed-off-by: Josef Gajdusek > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > index 0faa38a..58de718 100644 > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -359,6 +359,13 @@ > #size-cells = <0>; > }; > > + sid: eeprom at 01c14000 { > + compatible = "allwinner,sun4i-a10-sid"; > + reg = <0x01c14000 0x400>; The datasheet says it's 256 bytes wide, while the size here is of 1kB, is it intentional? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: robh@kernel.org (Rob Herring) Date: Mon, 23 Nov 2015 15:37:08 -0600 Subject: [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock In-Reply-To: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> References: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> Message-ID: <20151123213708.GA12308@rob-hp-laptop> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Nov 23, 2015 at 09:02:49AM +0100, Josef Gajdusek wrote: > This patch adds a driver for the THS clock which is present on the > Allwinner H3. > > Signed-off-by: Josef Gajdusek Acked-by: Rob Herring > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk-h3-ths.c | 98 +++++++++++++++++++++++ > 3 files changed, 100 insertions(+) > create mode 100644 drivers/clk/sunxi/clk-h3-ths.c > > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt > index 23e7bce..6d63b35 100644 > --- a/Documentation/devicetree/bindings/clock/sunxi.txt > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt > @@ -73,6 +73,7 @@ Required properties: > "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 > "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 > "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 > + "allwinner,sun8i-h3-ths-clk" - for THS on H3 > > Required properties for all clocks: > - reg : shall be the control register address for the clock. > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index f520af6..1bf8e1c 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -8,6 +8,7 @@ obj-y += clk-a10-hosc.o > obj-y += clk-a10-mod1.o > obj-y += clk-a10-pll2.o > obj-y += clk-a20-gmac.o > +obj-y += clk-h3-ths.o > obj-y += clk-mod0.o > obj-y += clk-simple-gates.o > obj-y += clk-sun8i-bus-gates.o > diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk-h3-ths.c > new file mode 100644 > index 0000000..663afc0 > --- /dev/null > +++ b/drivers/clk/sunxi/clk-h3-ths.c > @@ -0,0 +1,98 @@ > +/* > + * Sunxi THS clock driver > + * > + * Copyright (C) 2015 Josef Gajdusek > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include > +#include > +#include > + > +#define SUN8I_H3_THS_CLK_ENABLE 31 > +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0 > +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2 > + > +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock); > + > +static const struct clk_div_table sun8i_h3_ths_clk_table[] __initconst = { > + { .val = 0, .div = 1 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 6 }, > + { } /* sentinel */ > +}; > + > +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) > +{ > + struct clk *clk; > + struct clk_gate *gate; > + struct clk_divider *div; > + const char *parent; > + const char *clk_name = node->name; > + void __iomem *reg; > + int err; > + > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > + > + if (IS_ERR(reg)) > + return; > + > + gate = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!gate) > + goto err_unmap; > + > + div = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!div) > + goto err_gate_free; > + > + of_property_read_string(node, "clock-output-names", &clk_name); > + parent = of_clk_get_parent_name(node, 0); > + > + gate->reg = reg; > + gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE; > + gate->lock = &sun8i_h3_ths_clk_lock; > + > + div->reg = reg; > + div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT; > + div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH; > + div->table = sun8i_h3_ths_clk_table; > + div->lock = &sun8i_h3_ths_clk_lock; > + > + clk = clk_register_composite(NULL, clk_name, &parent, 1, > + NULL, NULL, > + &div->hw, &clk_divider_ops, > + &gate->hw, &clk_gate_ops, > + CLK_SET_RATE_PARENT); > + > + if (IS_ERR(clk)) > + goto err_div_free; > + > + err = of_clk_add_provider(node, of_clk_src_simple_get, clk); > + if (err) > + goto err_unregister_clk; > + > + return; > + > +err_unregister_clk: > + clk_unregister(clk); > +err_gate_free: > + kfree(gate); > +err_div_free: > + kfree(div); > +err_unmap: > + iounmap(reg); > +} > + > +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk", > + sun8i_h3_ths_clk_setup); > -- > 2.4.10 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: wens@csie.org (Chen-Yu Tsai) Date: Tue, 24 Nov 2015 11:13:13 +0800 Subject: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node In-Reply-To: <20151123124356.GW32142@lukather> References: <20151123124356.GW32142@lukather> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard wrote: > Hi, > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: >> Add a node describing the Security ID memory to the >> Allwinner H3 .dtsi file. >> >> Signed-off-by: Josef Gajdusek >> --- >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi >> index 0faa38a..58de718 100644 >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >> @@ -359,6 +359,13 @@ >> #size-cells = <0>; >> }; >> >> + sid: eeprom at 01c14000 { >> + compatible = "allwinner,sun4i-a10-sid"; >> + reg = <0x01c14000 0x400>; > > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > is it intentional? My H3 datasheet (v1.1) says its 1 kB wide. It'd be nice if Allwinner actually listed the "usable" E-fuse offsets and widths, instead of having us dig through the SDK code. Regards ChenYu From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 24 Nov 2015 07:38:09 +0100 Subject: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node In-Reply-To: References: <20151123124356.GW32142@lukather> Message-ID: <20151124063808.GB32142@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Nov 24, 2015 at 11:13:13AM +0800, Chen-Yu Tsai wrote: > Hi, > > On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard > wrote: > > Hi, > > > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > >> Add a node describing the Security ID memory to the > >> Allwinner H3 .dtsi file. > >> > >> Signed-off-by: Josef Gajdusek > >> --- > >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > >> 1 file changed, 7 insertions(+) > >> > >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > >> index 0faa38a..58de718 100644 > >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi > >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > >> @@ -359,6 +359,13 @@ > >> #size-cells = <0>; > >> }; > >> > >> + sid: eeprom at 01c14000 { > >> + compatible = "allwinner,sun4i-a10-sid"; > >> + reg = <0x01c14000 0x400>; > > > > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > > is it intentional? > > My H3 datasheet (v1.1) says its 1 kB wide. Is it? in the Security ID section, it is said to be 2kb == 256B wide. > It'd be nice if Allwinner actually listed the "usable" E-fuse > offsets and widths, instead of having us dig through the SDK code. Yep. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: wens@csie.org (Chen-Yu Tsai) Date: Tue, 24 Nov 2015 14:42:26 +0800 Subject: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node In-Reply-To: <20151124063808.GB32142@lukather> References: <20151123124356.GW32142@lukather> <20151124063808.GB32142@lukather> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Nov 24, 2015 at 2:38 PM, Maxime Ripard wrote: > On Tue, Nov 24, 2015 at 11:13:13AM +0800, Chen-Yu Tsai wrote: >> Hi, >> >> On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard >> wrote: >> > Hi, >> > >> > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: >> >> Add a node describing the Security ID memory to the >> >> Allwinner H3 .dtsi file. >> >> >> >> Signed-off-by: Josef Gajdusek >> >> --- >> >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ >> >> 1 file changed, 7 insertions(+) >> >> >> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi >> >> index 0faa38a..58de718 100644 >> >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi >> >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >> >> @@ -359,6 +359,13 @@ >> >> #size-cells = <0>; >> >> }; >> >> >> >> + sid: eeprom at 01c14000 { >> >> + compatible = "allwinner,sun4i-a10-sid"; >> >> + reg = <0x01c14000 0x400>; >> > >> > The datasheet says it's 256 bytes wide, while the size here is of 1kB, >> > is it intentional? >> >> My H3 datasheet (v1.1) says its 1 kB wide. > > Is it? in the Security ID section, it is said to be 2kb == 256B wide. Right. I was looking at the memory map. Maybe it's sparsely mapped? I guess we'll know soon. ChenYu >> It'd be nice if Allwinner actually listed the "usable" E-fuse >> offsets and widths, instead of having us dig through the SDK code. > > Yep. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 24 Nov 2015 07:38:30 +0100 Subject: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node In-Reply-To: <077cd975-1f91-40fe-ab05-2381e4fb6448@googlegroups.com> References: <20151123124356.GW32142@lukather> <077cd975-1f91-40fe-ab05-2381e4fb6448@googlegroups.com> Message-ID: <20151124063830.GC32142@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Nov 23, 2015 at 07:24:40PM -0800, Sugar Wu wrote: > I will give you the right widths as soon. Great, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 24 Nov 2015 08:26:13 +0100 Subject: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node In-Reply-To: References: <20151123124356.GW32142@lukather> <20151124063808.GB32142@lukather> Message-ID: <20151124072613.GF32142@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Nov 24, 2015 at 02:42:26PM +0800, Chen-Yu Tsai wrote: > On Tue, Nov 24, 2015 at 2:38 PM, Maxime Ripard > wrote: > > On Tue, Nov 24, 2015 at 11:13:13AM +0800, Chen-Yu Tsai wrote: > >> Hi, > >> > >> On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard > >> wrote: > >> > Hi, > >> > > >> > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > >> >> Add a node describing the Security ID memory to the > >> >> Allwinner H3 .dtsi file. > >> >> > >> >> Signed-off-by: Josef Gajdusek > >> >> --- > >> >> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > >> >> 1 file changed, 7 insertions(+) > >> >> > >> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi > >> >> index 0faa38a..58de718 100644 > >> >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi > >> >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > >> >> @@ -359,6 +359,13 @@ > >> >> #size-cells = <0>; > >> >> }; > >> >> > >> >> + sid: eeprom at 01c14000 { > >> >> + compatible = "allwinner,sun4i-a10-sid"; > >> >> + reg = <0x01c14000 0x400>; > >> > > >> > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > >> > is it intentional? > >> > >> My H3 datasheet (v1.1) says its 1 kB wide. > > > > Is it? in the Security ID section, it is said to be 2kb == 256B wide. > > Right. I was looking at the memory map. Maybe it's sparsely mapped? > I guess we'll know soon. If it is just like the A20, I think there's a few registers at the end to control the writes (that we don't use). Which means that the size of the fuses is smaller than the size of the mapped area (which also measn that our driver is broken making that assumption). Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 24 Nov 2015 09:43:42 +0100 Subject: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor In-Reply-To: References: Message-ID: <20151124084342.GJ32142@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Nov 23, 2015 at 09:02:50AM +0100, Josef Gajdusek wrote: > This patch adds support for the Sunxi thermal sensor on the Allwinner H3. You can drop the sunxi here. > Should be easily extendable for the A33/A83T/... as they have similar but > not completely identical sensors. > > Signed-off-by: Josef Gajdusek > --- > drivers/thermal/Kconfig | 7 + > drivers/thermal/Makefile | 1 + > drivers/thermal/sun8i_ths.c | 365 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 373 insertions(+) > create mode 100644 drivers/thermal/sun8i_ths.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index c463c89..2b41147 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config SUN8I_THS > + tristate "sun8i THS driver" > + depends on MACH_SUN8I > + depends on OF > + help > + Enable this to support thermal reporting on some newer Allwinner SoCs. > + > menu "Texas Instruments thermal drivers" > depends on ARCH_HAS_BANDGAP || COMPILE_TEST > source "drivers/thermal/ti-soc-thermal/Kconfig" > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index cfae6a6..227e1a1 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_SUN8I_THS) += sun8i_ths.o > diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c > new file mode 100644 > index 0000000..2c976ac > --- /dev/null > +++ b/drivers/thermal/sun8i_ths.c > @@ -0,0 +1,365 @@ > +/* > + * Sunxi THS driver sun8i Thermal Sensor Driver > + * Copyright (C) 2015 Josef Gajdusek > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + */ > + > +#include > +#include Are you using this header? > +#include > +#include > +#include You probably don't need this one too. > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define THS_H3_CTRL0 0x00 > +#define THS_H3_CTRL1 0x04 > +#define THS_H3_CDAT 0x14 > +#define THS_H3_CTRL2 0x40 > +#define THS_H3_INT_CTRL 0x44 > +#define THS_H3_STAT 0x48 > +#define THS_H3_ALARM_CTRL 0x50 > +#define THS_H3_SHUTDOWN_CTRL 0x60 > +#define THS_H3_FILTER 0x70 > +#define THS_H3_CDATA 0x74 > +#define THS_H3_DATA 0x80 > + > +#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS 0 > +#define THS_H3_CTRL0_SENSOR_ACQ0(x) \ > + ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS) > +#define THS_H3_CTRL1_ADC_CALI_EN_OFFS 17 > +#define THS_H3_CTRL1_ADC_CALI_EN \ > + BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS) > +#define THS_H3_CTRL1_OP_BIAS_OFFS 20 > +#define THS_H3_CTRL1_OP_BIAS(x) \ > + ((x) << THS_H3_CTRL1_OP_BIAS_OFFS) > +#define THS_H3_CTRL2_SENSE_EN_OFFS 0 > +#define THS_H3_CTRL2_SENSE_EN \ > + BIT(THS_H3_CTRL2_SENSE_EN_OFFS) > +#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS 16 > +#define THS_H3_CTRL2_SENSOR_ACQ1(x) \ > + ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS) > + > +#define THS_H3_INT_CTRL_ALARM_INT_EN_OFFS 0 > +#define THS_H3_INT_CTRL_ALARM_INT_EN \ > + BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS) > +#define THS_H3_INT_CTRL_SHUT_INT_EN_OFFS 4 > +#define THS_H3_INT_CTRL_SHUT_INT_EN \ > + BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS) > +#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS 8 > +#define THS_H3_INT_CTRL_DATA_IRQ_EN \ > + BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS) > +#define THS_H3_INT_CTRL_THERMAL_PER_OFFS 12 > +#define THS_H3_INT_CTRL_THERMAL_PER(x) \ > + ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS) > + > +#define THS_H3_STAT_ALARM_INT_STS_OFFS 0 > +#define THS_H3_STAT_ALARM_INT_STS \ > + BIT(THS_H3_STAT_ALARM_INT_STS_OFFS) > +#define THS_H3_STAT_SHUT_INT_STS_OFFS 4 > +#define THS_H3_STAT_SHUT_INT_STS \ > + BIT(THS_H3_STAT_SHUT_INT_STS_OFFS) > +#define THS_H3_STAT_DATA_IRQ_STS_OFFS 8 > +#define THS_H3_STAT_DATA_IRQ_STS \ > + BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS) > +#define THS_H3_STAT_ALARM_OFF_STS_OFFS 12 > +#define THS_H3_STAT_ALARM_OFF_STS \ > + BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS) > + > +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS 0 > +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST(x) \ > + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS) > +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS 16 > +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT(x) \ > + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS) > + > +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS 16 > +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT(x) \ > + ((x) << THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS) > + > +#define THS_H3_FILTER_TYPE_OFFS 0 > +#define THS_H3_FILTER_TYPE(x) \ > + ((x) << THS_H3_FILTER_TYPE_OFFS) > +#define THS_H3_FILTER_EN_OFFS 2 > +#define THS_H3_FILTER_EN \ > + BIT(THS_H3_FILTER_EN_OFFS) Are you using these offsets anywhere? > + > +#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0xff > +#define THS_H3_INT_CTRL_THERMAL_PER_VALUE 0x79 > +#define THS_H3_FILTER_TYPE_VALUE 0x2 > +#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f > + > +struct sun8i_ths_data { > + struct sun8i_ths_type *type; > + struct reset_control *reset; > + struct clk *clk; > + struct clk *busclk; > + void __iomem *regs; > + struct nvmem_cell *calcell; > + struct platform_device *pdev; > + struct thermal_zone_device *tzd; > +}; > + > +struct sun8i_ths_type { > + int (*init)(struct platform_device *, struct sun8i_ths_data *); > + int (*get_temp)(struct sun8i_ths_data *, int *out); > + void (*irq)(struct sun8i_ths_data *); > + void (*deinit)(struct sun8i_ths_data *); > +}; AFAIK, you never got back on why it was actually needed, instead of directly calling these functions. > +/* Formula and parameters from the Allwinner 3.4 kernel */ > +static int sun8i_ths_reg_to_temperature(s32 reg, int divisor, int constant) > +{ > + return constant - (reg * 1000000) / divisor; > +} > + > +static int sun8i_ths_get_temp(void *_data, int *out) > +{ > + struct sun8i_ths_data *data = _data; > + > + return data->type->get_temp(data, out); > +} > + > +static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data) > +{ > + struct sun8i_ths_data *data = _data; > + > + data->type->irq(data); > + thermal_zone_device_update(data->tzd); > + > + return IRQ_HANDLED; > +} > + > +static int sun8i_ths_h3_init(struct platform_device *pdev, > + struct sun8i_ths_data *data) > +{ > + int ret; > + size_t callen; > + s32 *caldata; > + > + data->busclk = devm_clk_get(&pdev->dev, "ahb"); > + if (IS_ERR(data->busclk)) { > + ret = PTR_ERR(data->busclk); > + dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret); > + return ret; > + } > + > + data->clk = devm_clk_get(&pdev->dev, "ths"); > + if (IS_ERR(data->clk)) { > + ret = PTR_ERR(data->clk); > + dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret); > + return ret; > + } > + > + data->reset = devm_reset_control_get(&pdev->dev, "ahb"); > + if (IS_ERR(data->reset)) { > + ret = PTR_ERR(data->reset); > + dev_err(&pdev->dev, "failed to get reset: %d\n", ret); > + return ret; > + } > + > + if (data->calcell) { > + caldata = nvmem_cell_read(data->calcell, &callen); > + if (IS_ERR(caldata)) > + return PTR_ERR(caldata); > + writel(be32_to_cpu(*caldata), data->regs + THS_H3_CDATA); > + kfree(caldata); > + } > + > + ret = clk_prepare_enable(data->busclk); > + if (ret) { > + dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret); > + return ret; > + } > + > + ret = clk_prepare_enable(data->clk); > + if (ret) { > + dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret); > + goto err_disable_bus; > + } > + > + ret = reset_control_deassert(data->reset); > + if (ret) { > + dev_err(&pdev->dev, "reset deassert failed: %d\n", ret); > + goto err_disable_ths; > + } > + > + /* The final sample period is calculated as follows: > + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) > + * > + * This results to about 1Hz with these settings. > + */ > + ret = clk_set_rate(data->clk, 4000000); I don't follow you here. You have a complicated math function, that has many input variables, and then, you just set the clock rate to a constant? > + if (ret) > + goto err_disable_ths; A new line here please > + writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE), > + data->regs + THS_H3_CTRL0); > + writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) | > + THS_H3_INT_CTRL_DATA_IRQ_EN, > + data->regs + THS_H3_INT_CTRL); > + writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE), > + data->regs + THS_H3_FILTER); > + writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) | > + THS_H3_CTRL2_SENSE_EN, > + data->regs + THS_H3_CTRL2); And here too. > + return 0; > + > +err_disable_ths: > + clk_disable_unprepare(data->clk); > +err_disable_bus: > + clk_disable_unprepare(data->busclk); > + > + return ret; > +} > + > +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *out) > +{ > + int val = readl(data->regs + THS_H3_DATA); > + *out = sun8i_ths_reg_to_temperature(val, 8253, 217000); > + return 0; Can't you just return the value directly? > +} > + > +static void sun8i_ths_h3_irq(struct sun8i_ths_data *data) > +{ > + writel(THS_H3_STAT_DATA_IRQ_STS | > + THS_H3_STAT_ALARM_INT_STS | > + THS_H3_STAT_ALARM_OFF_STS | > + THS_H3_STAT_SHUT_INT_STS, > + data->regs + THS_H3_STAT); So you're always clearing all the interrupts? Shouldn't you just clear only the interrupt you received? > +} > + > +static void sun8i_ths_h3_deinit(struct sun8i_ths_data *data) > +{ > + reset_control_assert(data->reset); > + clk_disable_unprepare(data->clk); > + clk_disable_unprepare(data->busclk); > +} > + > +static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = { > + .get_temp = sun8i_ths_get_temp, > +}; > + > +static const struct sun8i_ths_type sun8i_ths_device_h3 = { > + .init = sun8i_ths_h3_init, > + .get_temp = sun8i_ths_h3_get_temp, > + .irq = sun8i_ths_h3_irq, > + .deinit = sun8i_ths_h3_deinit, > +}; > + > +static const struct of_device_id sun8i_ths_id_table[] = { > + { > + .compatible = "allwinner,sun8i-h3-ths", > + .data = &sun8i_ths_device_h3, > + }, > + { > + /* sentinel */ > + }, > +}; > +MODULE_DEVICE_TABLE(of, sun8i_ths_id_table); > + > +static int sun8i_ths_probe(struct platform_device *pdev) > +{ > + struct device_node *np = pdev->dev.of_node; > + const struct of_device_id *match; > + struct sun8i_ths_data *data; > + struct resource *res; > + int ret; > + int irq; > + > + match = of_match_node(sun8i_ths_id_table, np); If you *really* need to (but I still don't really see why), you can use of_device_get_match_data here. > + > + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + data->type = (struct sun8i_ths_type *)match->data; > + data->pdev = pdev; > + > + data->calcell = devm_nvmem_cell_get(&pdev->dev, "calibration"); > + if (IS_ERR(data->calcell)) { > + if (PTR_ERR(data->calcell) == -EPROBE_DEFER) > + return PTR_ERR(data->calcell); New line > + data->calcell = NULL; /* No calibration register */ s/register/data/ ? > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + data->regs = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(data->regs)) { > + ret = PTR_ERR(data->regs); > + dev_err(&pdev->dev, > + "failed to ioremap THS registers: %d\n", ret); > + return ret; > + } > + > + irq = platform_get_irq(pdev, 0); > + if (irq < 0) { > + dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); > + return irq; > + } > + > + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, > + sun8i_ths_irq_thread, IRQF_ONESHOT, > + dev_name(&pdev->dev), data); Why a threaded irq? > + if (ret) > + return ret; > + > + ret = data->type->init(pdev, data); > + if (ret) > + return ret; > + > + data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, > + &sun8i_ths_thermal_ops); > + if (IS_ERR(data->tzd)) { > + ret = PTR_ERR(data->tzd); > + dev_err(&pdev->dev, "failed to register thermal zone: %d\n", > + ret); > + goto err_deinit; > + } > + > + platform_set_drvdata(pdev, data); > + return 0; > + > +err_deinit: > + data->type->deinit(data); > + return ret; > +} > + > +static int sun8i_ths_remove(struct platform_device *pdev) > +{ > + struct sun8i_ths_data *data = platform_get_drvdata(pdev); > + > + thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); > + data->type->deinit(data); > + return 0; > +} > + > +static struct platform_driver sun8i_ths_driver = { > + .probe = sun8i_ths_probe, > + .remove = sun8i_ths_remove, > + .driver = { > + .name = "sun8i_ths", > + .of_match_table = sun8i_ths_id_table, > + }, > +}; > + > +module_platform_driver(sun8i_ths_driver); > + > +MODULE_AUTHOR("Josef Gajdusek "); > +MODULE_DESCRIPTION("Sunxi THS driver"); Please change the description here too to match the header. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 24 Nov 2015 09:45:31 +0100 Subject: [PATCH v2 5/5] ARM: dts: sun8i: Add THS node to the H3 .dtsi In-Reply-To: <0fff612e26bf9cda9027a4175e16d25a0c2cc62c.1448263428.git.atx@atx.name> References: <0fff612e26bf9cda9027a4175e16d25a0c2cc62c.1448263428.git.atx@atx.name> Message-ID: <20151124084531.GK32142@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Nov 23, 2015 at 09:02:52AM +0100, Josef Gajdusek wrote: > + ths: ths at 01c25000 { > + #thermal-sensor-cells = <0>; > + compatible = "allwinner,sun8i-h3-ths"; > + reg = <0x01c25000 0x88>; The datasheet says the size is 0x400, any particular reason to have a Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 24 Nov 2015 10:32:02 +0100 Subject: [linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node In-Reply-To: References: <20151123124356.GW32142@lukather> Message-ID: <20151124093202.GL32142@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Nov 23, 2015 at 10:51:15PM -0800, Sugar Wu wrote: > On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: > > > > Hi, > > > > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > > > Add a node describing the Security ID memory to the > > > Allwinner H3 .dtsi file. > > > > > > Signed-off-by: Josef Gajdusek > > > > --- > > > arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > > > 1 file changed, 7 insertions(+) > > > > > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi > > b/arch/arm/boot/dts/sun8i-h3.dtsi > > > index 0faa38a..58de718 100644 > > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi > > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > > > @@ -359,6 +359,13 @@ > > > #size-cells = <0>; > > > }; > > > > > > + sid: eeprom at 01c14000 { > > > + compatible = "allwinner,sun4i-a10-sid"; > > > + reg = <0x01c14000 0x400>; > > > > The datasheet says it's 256 bytes wide, while the size here is of 1kB, > > is it intentional? > > SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space. > H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. Interesting, what is below the 0x200 registers? Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: shugelinux@gmail.com (Shuge) Date: Wed, 25 Nov 2015 09:22:56 +0800 Subject: [linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node In-Reply-To: <20151124093202.GL32142@lukather> References: <20151123124356.GW32142@lukather> <20151124093202.GL32142@lukather> Message-ID: <56550D70.6060109@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Monday, November 23, 2015 at 17:32 UTC+8, Maxime Ripard wrote: > On Mon, Nov 23, 2015 at 10:51:15PM -0800, Sugar Wu wrote: >> On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: >>> >>> Hi, >>> >>> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: >>>> Add a node describing the Security ID memory to the >>>> Allwinner H3 .dtsi file. >>>> >>>> Signed-off-by: Josef Gajdusek > >>>> --- >>>> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ >>>> 1 file changed, 7 insertions(+) >>>> >>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi >>> b/arch/arm/boot/dts/sun8i-h3.dtsi >>>> index 0faa38a..58de718 100644 >>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi >>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi >>>> @@ -359,6 +359,13 @@ >>>> #size-cells = <0>; >>>> }; >>>> >>>> + sid: eeprom at 01c14000 { >>>> + compatible = "allwinner,sun4i-a10-sid"; >>>> + reg = <0x01c14000 0x400>; >>> >>> The datasheet says it's 256 bytes wide, while the size here is of 1kB, >>> is it intentional? >> >> SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space. >> H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. > > Interesting, what is below the 0x200 registers? > Some control register about SID. offset: 0x40 SID Program/Read Control Register offset: 0x50 SID Program Key Value Register offset: 0x60 SID Read Key Value Register offset: 0x70 \ offset: 0x80 SJTAG Attribute 0 Register offset: 0x84 SJTAG Attribute 1 Register offset: 0x88 SJTAG Select Register offset: 0x90 SID Program Ctrol register for burned timing > > Thanks! > Maxime > From mboxrd@z Thu Jan 1 00:00:00 1970 From: atx@atx.name (Josef Gajdusek) Date: Wed, 25 Nov 2015 11:02:34 +0000 Subject: [linux-sunxi] Re: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor In-Reply-To: <20151124084342.GJ32142@lukather> References: <20151124084342.GJ32142@lukather> Message-ID: <0edf1031924124377647dfb0f62ec6c8@rainloop.atalax.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org November 24 2015 9:43 AM, "Maxime Ripard" wrote: > On Mon, Nov 23, 2015 at 09:02:50AM +0100, Josef Gajdusek wrote: > >> This patch adds support for the Sunxi thermal sensor on the Allwinner H3. > > You can drop the sunxi here. > >> Should be easily extendable for the A33/A83T/... as they have similar but >> not completely identical sensors. >> >> Signed-off-by: Josef Gajdusek >> --- >> drivers/thermal/Kconfig | 7 + >> drivers/thermal/Makefile | 1 + >> drivers/thermal/sun8i_ths.c | 365 ++++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 373 insertions(+) >> create mode 100644 drivers/thermal/sun8i_ths.c >> >> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig >> index c463c89..2b41147 100644 >> --- a/drivers/thermal/Kconfig >> +++ b/drivers/thermal/Kconfig >> @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL >> Thermal reporting device will provide temperature reading, >> programmable trip points and other information. >> >> +config SUN8I_THS >> + tristate "sun8i THS driver" >> + depends on MACH_SUN8I >> + depends on OF >> + help >> + Enable this to support thermal reporting on some newer Allwinner SoCs. >> + >> menu "Texas Instruments thermal drivers" >> depends on ARCH_HAS_BANDGAP || COMPILE_TEST >> source "drivers/thermal/ti-soc-thermal/Kconfig" >> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile >> index cfae6a6..227e1a1 100644 >> --- a/drivers/thermal/Makefile >> +++ b/drivers/thermal/Makefile >> @@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o >> obj-$(CONFIG_ST_THERMAL) += st/ >> obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o >> obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o >> +obj-$(CONFIG_SUN8I_THS) += sun8i_ths.o >> diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c >> new file mode 100644 >> index 0000000..2c976ac >> --- /dev/null >> +++ b/drivers/thermal/sun8i_ths.c >> @@ -0,0 +1,365 @@ >> +/* >> + * Sunxi THS driver > > sun8i Thermal Sensor Driver > >> + * Copyright (C) 2015 Josef Gajdusek >> + * >> + * This software is licensed under the terms of the GNU General Public >> + * License version 2, as published by the Free Software Foundation, and >> + * may be copied, distributed, and modified under those terms. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + */ >> + >> +#include >> +#include > > Are you using this header? > >> +#include >> +#include >> +#include > > You probably don't need this one too. > >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#define THS_H3_CTRL0 0x00 >> +#define THS_H3_CTRL1 0x04 >> +#define THS_H3_CDAT 0x14 >> +#define THS_H3_CTRL2 0x40 >> +#define THS_H3_INT_CTRL 0x44 >> +#define THS_H3_STAT 0x48 >> +#define THS_H3_ALARM_CTRL 0x50 >> +#define THS_H3_SHUTDOWN_CTRL 0x60 >> +#define THS_H3_FILTER 0x70 >> +#define THS_H3_CDATA 0x74 >> +#define THS_H3_DATA 0x80 >> + >> +#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS 0 >> +#define THS_H3_CTRL0_SENSOR_ACQ0(x) \ >> + ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS) >> +#define THS_H3_CTRL1_ADC_CALI_EN_OFFS 17 >> +#define THS_H3_CTRL1_ADC_CALI_EN \ >> + BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS) >> +#define THS_H3_CTRL1_OP_BIAS_OFFS 20 >> +#define THS_H3_CTRL1_OP_BIAS(x) \ >> + ((x) << THS_H3_CTRL1_OP_BIAS_OFFS) >> +#define THS_H3_CTRL2_SENSE_EN_OFFS 0 >> +#define THS_H3_CTRL2_SENSE_EN \ >> + BIT(THS_H3_CTRL2_SENSE_EN_OFFS) >> +#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS 16 >> +#define THS_H3_CTRL2_SENSOR_ACQ1(x) \ >> + ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS) >> + >> +#define THS_H3_INT_CTRL_ALARM_INT_EN_OFFS 0 >> +#define THS_H3_INT_CTRL_ALARM_INT_EN \ >> + BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS) >> +#define THS_H3_INT_CTRL_SHUT_INT_EN_OFFS 4 >> +#define THS_H3_INT_CTRL_SHUT_INT_EN \ >> + BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS) >> +#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS 8 >> +#define THS_H3_INT_CTRL_DATA_IRQ_EN \ >> + BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS) >> +#define THS_H3_INT_CTRL_THERMAL_PER_OFFS 12 >> +#define THS_H3_INT_CTRL_THERMAL_PER(x) \ >> + ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS) >> + >> +#define THS_H3_STAT_ALARM_INT_STS_OFFS 0 >> +#define THS_H3_STAT_ALARM_INT_STS \ >> + BIT(THS_H3_STAT_ALARM_INT_STS_OFFS) >> +#define THS_H3_STAT_SHUT_INT_STS_OFFS 4 >> +#define THS_H3_STAT_SHUT_INT_STS \ >> + BIT(THS_H3_STAT_SHUT_INT_STS_OFFS) >> +#define THS_H3_STAT_DATA_IRQ_STS_OFFS 8 >> +#define THS_H3_STAT_DATA_IRQ_STS \ >> + BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS) >> +#define THS_H3_STAT_ALARM_OFF_STS_OFFS 12 >> +#define THS_H3_STAT_ALARM_OFF_STS \ >> + BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS) >> + >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS 0 >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST(x) \ >> + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS) >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS 16 >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT(x) \ >> + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS) >> + >> +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS 16 >> +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT(x) \ >> + ((x) << THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS) >> + >> +#define THS_H3_FILTER_TYPE_OFFS 0 >> +#define THS_H3_FILTER_TYPE(x) \ >> + ((x) << THS_H3_FILTER_TYPE_OFFS) >> +#define THS_H3_FILTER_EN_OFFS 2 >> +#define THS_H3_FILTER_EN \ >> + BIT(THS_H3_FILTER_EN_OFFS) > > Are you using these offsets anywhere? >> + >> +#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0xff >> +#define THS_H3_INT_CTRL_THERMAL_PER_VALUE 0x79 >> +#define THS_H3_FILTER_TYPE_VALUE 0x2 >> +#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f >> + >> +struct sun8i_ths_data { >> + struct sun8i_ths_type *type; >> + struct reset_control *reset; >> + struct clk *clk; >> + struct clk *busclk; >> + void __iomem *regs; >> + struct nvmem_cell *calcell; >> + struct platform_device *pdev; >> + struct thermal_zone_device *tzd; >> +}; >> + >> +struct sun8i_ths_type { >> + int (*init)(struct platform_device *, struct sun8i_ths_data *); >> + int (*get_temp)(struct sun8i_ths_data *, int *out); >> + void (*irq)(struct sun8i_ths_data *); >> + void (*deinit)(struct sun8i_ths_data *); >> +}; > > AFAIK, you never got back on why it was actually needed, instead of > directly calling these functions. It is preparation for supporting the other SoCs with THS as they have slightly different register layouts and thus cannot be controlled by the same code. >> +/* Formula and parameters from the Allwinner 3.4 kernel */ >> +static int sun8i_ths_reg_to_temperature(s32 reg, int divisor, int constant) >> +{ >> + return constant - (reg * 1000000) / divisor; >> +} >> + >> +static int sun8i_ths_get_temp(void *_data, int *out) >> +{ >> + struct sun8i_ths_data *data = _data; >> + >> + return data->type->get_temp(data, out); >> +} >> + >> +static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data) >> +{ >> + struct sun8i_ths_data *data = _data; >> + >> + data->type->irq(data); >> + thermal_zone_device_update(data->tzd); >> + >> + return IRQ_HANDLED; >> +} >> + >> +static int sun8i_ths_h3_init(struct platform_device *pdev, >> + struct sun8i_ths_data *data) >> +{ >> + int ret; >> + size_t callen; >> + s32 *caldata; >> + >> + data->busclk = devm_clk_get(&pdev->dev, "ahb"); >> + if (IS_ERR(data->busclk)) { >> + ret = PTR_ERR(data->busclk); >> + dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret); >> + return ret; >> + } >> + >> + data->clk = devm_clk_get(&pdev->dev, "ths"); >> + if (IS_ERR(data->clk)) { >> + ret = PTR_ERR(data->clk); >> + dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret); >> + return ret; >> + } >> + >> + data->reset = devm_reset_control_get(&pdev->dev, "ahb"); >> + if (IS_ERR(data->reset)) { >> + ret = PTR_ERR(data->reset); >> + dev_err(&pdev->dev, "failed to get reset: %d\n", ret); >> + return ret; >> + } >> + >> + if (data->calcell) { >> + caldata = nvmem_cell_read(data->calcell, &callen); >> + if (IS_ERR(caldata)) >> + return PTR_ERR(caldata); >> + writel(be32_to_cpu(*caldata), data->regs + THS_H3_CDATA); >> + kfree(caldata); >> + } >> + >> + ret = clk_prepare_enable(data->busclk); >> + if (ret) { >> + dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret); >> + return ret; >> + } >> + >> + ret = clk_prepare_enable(data->clk); >> + if (ret) { >> + dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret); >> + goto err_disable_bus; >> + } >> + >> + ret = reset_control_deassert(data->reset); >> + if (ret) { >> + dev_err(&pdev->dev, "reset deassert failed: %d\n", ret); >> + goto err_disable_ths; >> + } >> + >> + /* The final sample period is calculated as follows: >> + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) >> + * >> + * This results to about 1Hz with these settings. >> + */ >> + ret = clk_set_rate(data->clk, 4000000); > > I don't follow you here. You have a complicated math function, that > has many input variables, and then, you just set the clock rate to a > constant? How should this be handled then? I guess the sampling rate could be set in the device tree and then the values calculated, but none of the other thermal drivers seem to have configurable sample rate. >> + if (ret) >> + goto err_disable_ths; > > A new line here please > >> + writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE), >> + data->regs + THS_H3_CTRL0); >> + writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) | >> + THS_H3_INT_CTRL_DATA_IRQ_EN, >> + data->regs + THS_H3_INT_CTRL); >> + writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE), >> + data->regs + THS_H3_FILTER); >> + writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) | >> + THS_H3_CTRL2_SENSE_EN, >> + data->regs + THS_H3_CTRL2); > > And here too. > >> + return 0; >> + >> +err_disable_ths: >> + clk_disable_unprepare(data->clk); >> +err_disable_bus: >> + clk_disable_unprepare(data->busclk); >> + >> + return ret; >> +} >> + >> +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *out) >> +{ >> + int val = readl(data->regs + THS_H3_DATA); >> + *out = sun8i_ths_reg_to_temperature(val, 8253, 217000); >> + return 0; > > Can't you just return the value directly? I did that in the v1, clabbe.montjoie suggested to use temp variable to avoid column wrap. >> +} >> + >> +static void sun8i_ths_h3_irq(struct sun8i_ths_data *data) >> +{ >> + writel(THS_H3_STAT_DATA_IRQ_STS | >> + THS_H3_STAT_ALARM_INT_STS | >> + THS_H3_STAT_ALARM_OFF_STS | >> + THS_H3_STAT_SHUT_INT_STS, >> + data->regs + THS_H3_STAT); > > So you're always clearing all the interrupts? Shouldn't you just clear > only the interrupt you received? > >> +} >> + >> +static void sun8i_ths_h3_deinit(struct sun8i_ths_data *data) >> +{ >> + reset_control_assert(data->reset); >> + clk_disable_unprepare(data->clk); >> + clk_disable_unprepare(data->busclk); >> +} >> + >> +static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = { >> + .get_temp = sun8i_ths_get_temp, >> +}; >> + >> +static const struct sun8i_ths_type sun8i_ths_device_h3 = { >> + .init = sun8i_ths_h3_init, >> + .get_temp = sun8i_ths_h3_get_temp, >> + .irq = sun8i_ths_h3_irq, >> + .deinit = sun8i_ths_h3_deinit, >> +}; >> + >> +static const struct of_device_id sun8i_ths_id_table[] = { >> + { >> + .compatible = "allwinner,sun8i-h3-ths", >> + .data = &sun8i_ths_device_h3, >> + }, >> + { >> + /* sentinel */ >> + }, >> +}; >> +MODULE_DEVICE_TABLE(of, sun8i_ths_id_table); >> + >> +static int sun8i_ths_probe(struct platform_device *pdev) >> +{ >> + struct device_node *np = pdev->dev.of_node; >> + const struct of_device_id *match; >> + struct sun8i_ths_data *data; >> + struct resource *res; >> + int ret; >> + int irq; >> + >> + match = of_match_node(sun8i_ths_id_table, np); > > If you *really* need to (but I still don't really see why), you can > use of_device_get_match_data here. > >> + >> + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); >> + if (!data) >> + return -ENOMEM; >> + >> + data->type = (struct sun8i_ths_type *)match->data; >> + data->pdev = pdev; >> + >> + data->calcell = devm_nvmem_cell_get(&pdev->dev, "calibration"); >> + if (IS_ERR(data->calcell)) { >> + if (PTR_ERR(data->calcell) == -EPROBE_DEFER) >> + return PTR_ERR(data->calcell); > > New line > >> + data->calcell = NULL; /* No calibration register */ > > s/register/data/ ? > >> + } >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + data->regs = devm_ioremap_resource(&pdev->dev, res); >> + if (IS_ERR(data->regs)) { >> + ret = PTR_ERR(data->regs); >> + dev_err(&pdev->dev, >> + "failed to ioremap THS registers: %d\n", ret); >> + return ret; >> + } >> + >> + irq = platform_get_irq(pdev, 0); >> + if (irq < 0) { >> + dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); >> + return irq; >> + } >> + >> + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, >> + sun8i_ths_irq_thread, IRQF_ONESHOT, >> + dev_name(&pdev->dev), data); > > Why a threaded irq? I thought threaded IRQs are preferred? Other thermal drivers use them too. I am also not really sure thermal_zone_device_update() can even be called in interrupt context. >> + if (ret) >> + return ret; >> + >> + ret = data->type->init(pdev, data); >> + if (ret) >> + return ret; >> + >> + data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, >> + &sun8i_ths_thermal_ops); >> + if (IS_ERR(data->tzd)) { >> + ret = PTR_ERR(data->tzd); >> + dev_err(&pdev->dev, "failed to register thermal zone: %d\n", >> + ret); >> + goto err_deinit; >> + } >> + >> + platform_set_drvdata(pdev, data); >> + return 0; >> + >> +err_deinit: >> + data->type->deinit(data); >> + return ret; >> +} >> + >> +static int sun8i_ths_remove(struct platform_device *pdev) >> +{ >> + struct sun8i_ths_data *data = platform_get_drvdata(pdev); >> + >> + thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); >> + data->type->deinit(data); >> + return 0; >> +} >> + >> +static struct platform_driver sun8i_ths_driver = { >> + .probe = sun8i_ths_probe, >> + .remove = sun8i_ths_remove, >> + .driver = { >> + .name = "sun8i_ths", >> + .of_match_table = sun8i_ths_id_table, >> + }, >> +}; >> + >> +module_platform_driver(sun8i_ths_driver); >> + >> +MODULE_AUTHOR("Josef Gajdusek "); >> +MODULE_DESCRIPTION("Sunxi THS driver"); > > Please change the description here too to match the header. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to > linux-sunxi+unsubscribe at googlegroups.com. > For more options, visit https://groups.google.com/d/optout. Josef Gajdusek From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Mon, 30 Nov 2015 20:58:23 +0100 Subject: [linux-sunxi] Re: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor In-Reply-To: <0edf1031924124377647dfb0f62ec6c8@rainloop.atalax.net> References: <20151124084342.GJ32142@lukather> <0edf1031924124377647dfb0f62ec6c8@rainloop.atalax.net> Message-ID: <20151130195823.GE3664@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Nov 25, 2015 at 11:02:34AM +0000, Josef Gajdusek wrote: > >> +struct sun8i_ths_type { > >> + int (*init)(struct platform_device *, struct sun8i_ths_data *); > >> + int (*get_temp)(struct sun8i_ths_data *, int *out); > >> + void (*irq)(struct sun8i_ths_data *); > >> + void (*deinit)(struct sun8i_ths_data *); > >> +}; > > > > AFAIK, you never got back on why it was actually needed, instead of > > directly calling these functions. > > It is preparation for supporting the other SoCs with THS as they have > slightly different register layouts and thus cannot be controlled by the > same code. Do you have support and / or informations on what's going to be needed for these other SoCs yet? Which SoCs are we talking about? > >> + /* The final sample period is calculated as follows: > >> + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) > >> + * > >> + * This results to about 1Hz with these settings. > >> + */ > >> + ret = clk_set_rate(data->clk, 4000000); > > > > I don't follow you here. You have a complicated math function, that > > has many input variables, and then, you just set the clock rate to a > > constant? > > How should this be handled then? I guess the sampling rate could > be set in the device tree and then the values calculated, but none > of the other thermal drivers seem to have configurable sample rate. I don't know, I would have expected some actual computation, like a function taking the frequency as a parameter and returning the clock rate. At least that way we now what we're doing and which part might change and which will not. But you do not need to change the sample rate itself. > >> +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *out) > >> +{ > >> + int val = readl(data->regs + THS_H3_DATA); > >> + *out = sun8i_ths_reg_to_temperature(val, 8253, 217000); > >> + return 0; > > > > Can't you just return the value directly? > > I did that in the v1, clabbe.montjoie suggested to use temp variable to > avoid column wrap. I was talking about the out pointer. Can the value not be returned? > >> + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, > >> + sun8i_ths_irq_thread, IRQF_ONESHOT, > >> + dev_name(&pdev->dev), data); > > > > Why a threaded irq? > > I thought threaded IRQs are preferred? Other thermal drivers > use them too. It's close to pointless in this case. You're not doing much more than what the default handler will do anyway, and you avoid scheduling a thread doing so. And other thermal drivers use a regular interrupt handler too :) > I am also not really sure thermal_zone_device_update() can even be > called in interrupt context. I can't really tell on this one. Judging from a quick look, I can't see anything that could prevent it, and since others are using it, it seems doable. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 1 Dec 2015 09:41:17 +0100 Subject: [linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node In-Reply-To: <56550D70.6060109@gmail.com> References: <20151123124356.GW32142@lukather> <20151124093202.GL32142@lukather> <56550D70.6060109@gmail.com> Message-ID: <20151201084117.GB29263@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, On Wed, Nov 25, 2015 at 09:22:56AM +0800, Shuge wrote: > On Monday, November 23, 2015 at 17:32 UTC+8, Maxime Ripard wrote: > > On Mon, Nov 23, 2015 at 10:51:15PM -0800, Sugar Wu wrote: > >> On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote: > >>> > >>> Hi, > >>> > >>> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: > >>>> Add a node describing the Security ID memory to the > >>>> Allwinner H3 .dtsi file. > >>>> > >>>> Signed-off-by: Josef Gajdusek > > >>>> --- > >>>> arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++++++ > >>>> 1 file changed, 7 insertions(+) > >>>> > >>>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi > >>> b/arch/arm/boot/dts/sun8i-h3.dtsi > >>>> index 0faa38a..58de718 100644 > >>>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi > >>>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > >>>> @@ -359,6 +359,13 @@ > >>>> #size-cells = <0>; > >>>> }; > >>>> > >>>> + sid: eeprom at 01c14000 { > >>>> + compatible = "allwinner,sun4i-a10-sid"; > >>>> + reg = <0x01c14000 0x400>; > >>> > >>> The datasheet says it's 256 bytes wide, while the size here is of 1kB, > >>> is it intentional? > >> > >> SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space. > >> H3 efuse space is SID_SRAM, its range is 0x01c14200 ~ +0x100. > > > > Interesting, what is below the 0x200 registers? > > > Some control register about SID. > offset: 0x40 SID Program/Read Control Register > offset: 0x50 SID Program Key Value Register > offset: 0x60 SID Read Key Value Register > offset: 0x70 \ > offset: 0x80 SJTAG Attribute 0 Register > offset: 0x84 SJTAG Attribute 1 Register > offset: 0x88 SJTAG Select Register > offset: 0x90 SID Program Ctrol register for burned timing Thanks! I guess the layout changed a bit from the A10 and alikes then. Anyway, we should expose only to the nvmem framework the actual eeprom space, so from 0x200 to 0x300 from what you're saying (just like we should only expose the first 4 bytes in the A10 / A20) Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754198AbbKWJQY (ORCPT ); Mon, 23 Nov 2015 04:16:24 -0500 Received: from mail-wm0-f52.google.com ([74.125.82.52]:37602 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750853AbbKWJQW (ORCPT ); Mon, 23 Nov 2015 04:16:22 -0500 Date: Mon, 23 Nov 2015 10:16:18 +0100 From: LABBE Corentin To: Josef Gajdusek Cc: linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [linux-sunxi] [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock Message-ID: <20151123091618.GA19570@Red> References: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <077fddc9c8d41d4cf55b1dd1c7180c4adee0fce4.1448263428.git.atx@atx.name> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 23, 2015 at 09:02:49AM +0100, Josef Gajdusek wrote: > This patch adds a driver for the THS clock which is present on the > Allwinner H3. > > Signed-off-by: Josef Gajdusek > --- Hello Just a minor comment below. > +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) > +{ > + struct clk *clk; > + struct clk_gate *gate; > + struct clk_divider *div; > + const char *parent; > + const char *clk_name = node->name; > + void __iomem *reg; > + int err; > + > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > + > + if (IS_ERR(reg)) > + return; > + > + gate = kzalloc(sizeof(*gate), GFP_KERNEL); > + if (!gate) > + goto err_unmap; > + > + div = kzalloc(sizeof(*gate), GFP_KERNEL); copy/paste error, you mean sizeof(*div) ? > + if (!div) > + goto err_gate_free; > + > + of_property_read_string(node, "clock-output-names", &clk_name); Regards From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753031AbbKYLLA (ORCPT ); Wed, 25 Nov 2015 06:11:00 -0500 Received: from [31.31.75.104] ([31.31.75.104]:60960 "EHLO twilight.atalax.net" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1752669AbbKYLK4 convert rfc822-to-8bit (ORCPT ); Wed, 25 Nov 2015 06:10:56 -0500 X-Greylist: delayed 505 seconds by postgrey-1.27 at vger.kernel.org; Wed, 25 Nov 2015 06:10:55 EST Mime-Version: 1.0 Date: Wed, 25 Nov 2015 11:02:34 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Message-ID: <0edf1031924124377647dfb0f62ec6c8@rainloop.atalax.net> X-Mailer: RainLoop/1.8.1.263 From: "Josef Gajdusek" Subject: Re: [linux-sunxi] Re: [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor To: maxime.ripard@free-electrons.com Cc: linux-sunxi@googlegroups.com, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, gpatchesrdh@mveas.com, mturquette@linaro.org, hdegoede@redhat.com, sboyd@codeaurora.org, mturquette@baylibre.com, emilio@elopez.com.ar, linux@arm.linux.org.uk, edubezval@gmail.com, rui.zhang@intel.com, wens@csie.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org In-Reply-To: <20151124084342.GJ32142@lukather> References: <20151124084342.GJ32142@lukather> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org November 24 2015 9:43 AM, "Maxime Ripard" wrote: > On Mon, Nov 23, 2015 at 09:02:50AM +0100, Josef Gajdusek wrote: > >> This patch adds support for the Sunxi thermal sensor on the Allwinner H3. > > You can drop the sunxi here. > >> Should be easily extendable for the A33/A83T/... as they have similar but >> not completely identical sensors. >> >> Signed-off-by: Josef Gajdusek >> --- >> drivers/thermal/Kconfig | 7 + >> drivers/thermal/Makefile | 1 + >> drivers/thermal/sun8i_ths.c | 365 ++++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 373 insertions(+) >> create mode 100644 drivers/thermal/sun8i_ths.c >> >> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig >> index c463c89..2b41147 100644 >> --- a/drivers/thermal/Kconfig >> +++ b/drivers/thermal/Kconfig >> @@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL >> Thermal reporting device will provide temperature reading, >> programmable trip points and other information. >> >> +config SUN8I_THS >> + tristate "sun8i THS driver" >> + depends on MACH_SUN8I >> + depends on OF >> + help >> + Enable this to support thermal reporting on some newer Allwinner SoCs. >> + >> menu "Texas Instruments thermal drivers" >> depends on ARCH_HAS_BANDGAP || COMPILE_TEST >> source "drivers/thermal/ti-soc-thermal/Kconfig" >> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile >> index cfae6a6..227e1a1 100644 >> --- a/drivers/thermal/Makefile >> +++ b/drivers/thermal/Makefile >> @@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o >> obj-$(CONFIG_ST_THERMAL) += st/ >> obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o >> obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o >> +obj-$(CONFIG_SUN8I_THS) += sun8i_ths.o >> diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c >> new file mode 100644 >> index 0000000..2c976ac >> --- /dev/null >> +++ b/drivers/thermal/sun8i_ths.c >> @@ -0,0 +1,365 @@ >> +/* >> + * Sunxi THS driver > > sun8i Thermal Sensor Driver > >> + * Copyright (C) 2015 Josef Gajdusek >> + * >> + * This software is licensed under the terms of the GNU General Public >> + * License version 2, as published by the Free Software Foundation, and >> + * may be copied, distributed, and modified under those terms. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + */ >> + >> +#include >> +#include > > Are you using this header? > >> +#include >> +#include >> +#include > > You probably don't need this one too. > >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#define THS_H3_CTRL0 0x00 >> +#define THS_H3_CTRL1 0x04 >> +#define THS_H3_CDAT 0x14 >> +#define THS_H3_CTRL2 0x40 >> +#define THS_H3_INT_CTRL 0x44 >> +#define THS_H3_STAT 0x48 >> +#define THS_H3_ALARM_CTRL 0x50 >> +#define THS_H3_SHUTDOWN_CTRL 0x60 >> +#define THS_H3_FILTER 0x70 >> +#define THS_H3_CDATA 0x74 >> +#define THS_H3_DATA 0x80 >> + >> +#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS 0 >> +#define THS_H3_CTRL0_SENSOR_ACQ0(x) \ >> + ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS) >> +#define THS_H3_CTRL1_ADC_CALI_EN_OFFS 17 >> +#define THS_H3_CTRL1_ADC_CALI_EN \ >> + BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS) >> +#define THS_H3_CTRL1_OP_BIAS_OFFS 20 >> +#define THS_H3_CTRL1_OP_BIAS(x) \ >> + ((x) << THS_H3_CTRL1_OP_BIAS_OFFS) >> +#define THS_H3_CTRL2_SENSE_EN_OFFS 0 >> +#define THS_H3_CTRL2_SENSE_EN \ >> + BIT(THS_H3_CTRL2_SENSE_EN_OFFS) >> +#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS 16 >> +#define THS_H3_CTRL2_SENSOR_ACQ1(x) \ >> + ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS) >> + >> +#define THS_H3_INT_CTRL_ALARM_INT_EN_OFFS 0 >> +#define THS_H3_INT_CTRL_ALARM_INT_EN \ >> + BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS) >> +#define THS_H3_INT_CTRL_SHUT_INT_EN_OFFS 4 >> +#define THS_H3_INT_CTRL_SHUT_INT_EN \ >> + BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS) >> +#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS 8 >> +#define THS_H3_INT_CTRL_DATA_IRQ_EN \ >> + BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS) >> +#define THS_H3_INT_CTRL_THERMAL_PER_OFFS 12 >> +#define THS_H3_INT_CTRL_THERMAL_PER(x) \ >> + ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS) >> + >> +#define THS_H3_STAT_ALARM_INT_STS_OFFS 0 >> +#define THS_H3_STAT_ALARM_INT_STS \ >> + BIT(THS_H3_STAT_ALARM_INT_STS_OFFS) >> +#define THS_H3_STAT_SHUT_INT_STS_OFFS 4 >> +#define THS_H3_STAT_SHUT_INT_STS \ >> + BIT(THS_H3_STAT_SHUT_INT_STS_OFFS) >> +#define THS_H3_STAT_DATA_IRQ_STS_OFFS 8 >> +#define THS_H3_STAT_DATA_IRQ_STS \ >> + BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS) >> +#define THS_H3_STAT_ALARM_OFF_STS_OFFS 12 >> +#define THS_H3_STAT_ALARM_OFF_STS \ >> + BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS) >> + >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS 0 >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HYST(x) \ >> + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS) >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS 16 >> +#define THS_H3_ALARM_CTRL_ALARM0_T_HOT(x) \ >> + ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS) >> + >> +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS 16 >> +#define THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT(x) \ >> + ((x) << THS_H3_SHUTDOWN_CTRL_SHUT0_T_HOT_OFFS) >> + >> +#define THS_H3_FILTER_TYPE_OFFS 0 >> +#define THS_H3_FILTER_TYPE(x) \ >> + ((x) << THS_H3_FILTER_TYPE_OFFS) >> +#define THS_H3_FILTER_EN_OFFS 2 >> +#define THS_H3_FILTER_EN \ >> + BIT(THS_H3_FILTER_EN_OFFS) > > Are you using these offsets anywhere? >> + >> +#define THS_H3_CTRL0_SENSOR_ACQ0_VALUE 0xff >> +#define THS_H3_INT_CTRL_THERMAL_PER_VALUE 0x79 >> +#define THS_H3_FILTER_TYPE_VALUE 0x2 >> +#define THS_H3_CTRL2_SENSOR_ACQ1_VALUE 0x3f >> + >> +struct sun8i_ths_data { >> + struct sun8i_ths_type *type; >> + struct reset_control *reset; >> + struct clk *clk; >> + struct clk *busclk; >> + void __iomem *regs; >> + struct nvmem_cell *calcell; >> + struct platform_device *pdev; >> + struct thermal_zone_device *tzd; >> +}; >> + >> +struct sun8i_ths_type { >> + int (*init)(struct platform_device *, struct sun8i_ths_data *); >> + int (*get_temp)(struct sun8i_ths_data *, int *out); >> + void (*irq)(struct sun8i_ths_data *); >> + void (*deinit)(struct sun8i_ths_data *); >> +}; > > AFAIK, you never got back on why it was actually needed, instead of > directly calling these functions. It is preparation for supporting the other SoCs with THS as they have slightly different register layouts and thus cannot be controlled by the same code. >> +/* Formula and parameters from the Allwinner 3.4 kernel */ >> +static int sun8i_ths_reg_to_temperature(s32 reg, int divisor, int constant) >> +{ >> + return constant - (reg * 1000000) / divisor; >> +} >> + >> +static int sun8i_ths_get_temp(void *_data, int *out) >> +{ >> + struct sun8i_ths_data *data = _data; >> + >> + return data->type->get_temp(data, out); >> +} >> + >> +static irqreturn_t sun8i_ths_irq_thread(int irq, void *_data) >> +{ >> + struct sun8i_ths_data *data = _data; >> + >> + data->type->irq(data); >> + thermal_zone_device_update(data->tzd); >> + >> + return IRQ_HANDLED; >> +} >> + >> +static int sun8i_ths_h3_init(struct platform_device *pdev, >> + struct sun8i_ths_data *data) >> +{ >> + int ret; >> + size_t callen; >> + s32 *caldata; >> + >> + data->busclk = devm_clk_get(&pdev->dev, "ahb"); >> + if (IS_ERR(data->busclk)) { >> + ret = PTR_ERR(data->busclk); >> + dev_err(&pdev->dev, "failed to get ahb clk: %d\n", ret); >> + return ret; >> + } >> + >> + data->clk = devm_clk_get(&pdev->dev, "ths"); >> + if (IS_ERR(data->clk)) { >> + ret = PTR_ERR(data->clk); >> + dev_err(&pdev->dev, "failed to get ths clk: %d\n", ret); >> + return ret; >> + } >> + >> + data->reset = devm_reset_control_get(&pdev->dev, "ahb"); >> + if (IS_ERR(data->reset)) { >> + ret = PTR_ERR(data->reset); >> + dev_err(&pdev->dev, "failed to get reset: %d\n", ret); >> + return ret; >> + } >> + >> + if (data->calcell) { >> + caldata = nvmem_cell_read(data->calcell, &callen); >> + if (IS_ERR(caldata)) >> + return PTR_ERR(caldata); >> + writel(be32_to_cpu(*caldata), data->regs + THS_H3_CDATA); >> + kfree(caldata); >> + } >> + >> + ret = clk_prepare_enable(data->busclk); >> + if (ret) { >> + dev_err(&pdev->dev, "failed to enable bus clk: %d\n", ret); >> + return ret; >> + } >> + >> + ret = clk_prepare_enable(data->clk); >> + if (ret) { >> + dev_err(&pdev->dev, "failed to enable ths clk: %d\n", ret); >> + goto err_disable_bus; >> + } >> + >> + ret = reset_control_deassert(data->reset); >> + if (ret) { >> + dev_err(&pdev->dev, "reset deassert failed: %d\n", ret); >> + goto err_disable_ths; >> + } >> + >> + /* The final sample period is calculated as follows: >> + * (THERMAL_PER + 1) * 4096 / f_clk * 2^(FILTER_TYPE + 1) >> + * >> + * This results to about 1Hz with these settings. >> + */ >> + ret = clk_set_rate(data->clk, 4000000); > > I don't follow you here. You have a complicated math function, that > has many input variables, and then, you just set the clock rate to a > constant? How should this be handled then? I guess the sampling rate could be set in the device tree and then the values calculated, but none of the other thermal drivers seem to have configurable sample rate. >> + if (ret) >> + goto err_disable_ths; > > A new line here please > >> + writel(THS_H3_CTRL0_SENSOR_ACQ0(THS_H3_CTRL0_SENSOR_ACQ0_VALUE), >> + data->regs + THS_H3_CTRL0); >> + writel(THS_H3_INT_CTRL_THERMAL_PER(THS_H3_INT_CTRL_THERMAL_PER_VALUE) | >> + THS_H3_INT_CTRL_DATA_IRQ_EN, >> + data->regs + THS_H3_INT_CTRL); >> + writel(THS_H3_FILTER_EN | THS_H3_FILTER_TYPE(THS_H3_FILTER_TYPE_VALUE), >> + data->regs + THS_H3_FILTER); >> + writel(THS_H3_CTRL2_SENSOR_ACQ1(THS_H3_CTRL2_SENSOR_ACQ1_VALUE) | >> + THS_H3_CTRL2_SENSE_EN, >> + data->regs + THS_H3_CTRL2); > > And here too. > >> + return 0; >> + >> +err_disable_ths: >> + clk_disable_unprepare(data->clk); >> +err_disable_bus: >> + clk_disable_unprepare(data->busclk); >> + >> + return ret; >> +} >> + >> +static int sun8i_ths_h3_get_temp(struct sun8i_ths_data *data, int *out) >> +{ >> + int val = readl(data->regs + THS_H3_DATA); >> + *out = sun8i_ths_reg_to_temperature(val, 8253, 217000); >> + return 0; > > Can't you just return the value directly? I did that in the v1, clabbe.montjoie suggested to use temp variable to avoid column wrap. >> +} >> + >> +static void sun8i_ths_h3_irq(struct sun8i_ths_data *data) >> +{ >> + writel(THS_H3_STAT_DATA_IRQ_STS | >> + THS_H3_STAT_ALARM_INT_STS | >> + THS_H3_STAT_ALARM_OFF_STS | >> + THS_H3_STAT_SHUT_INT_STS, >> + data->regs + THS_H3_STAT); > > So you're always clearing all the interrupts? Shouldn't you just clear > only the interrupt you received? > >> +} >> + >> +static void sun8i_ths_h3_deinit(struct sun8i_ths_data *data) >> +{ >> + reset_control_assert(data->reset); >> + clk_disable_unprepare(data->clk); >> + clk_disable_unprepare(data->busclk); >> +} >> + >> +static const struct thermal_zone_of_device_ops sun8i_ths_thermal_ops = { >> + .get_temp = sun8i_ths_get_temp, >> +}; >> + >> +static const struct sun8i_ths_type sun8i_ths_device_h3 = { >> + .init = sun8i_ths_h3_init, >> + .get_temp = sun8i_ths_h3_get_temp, >> + .irq = sun8i_ths_h3_irq, >> + .deinit = sun8i_ths_h3_deinit, >> +}; >> + >> +static const struct of_device_id sun8i_ths_id_table[] = { >> + { >> + .compatible = "allwinner,sun8i-h3-ths", >> + .data = &sun8i_ths_device_h3, >> + }, >> + { >> + /* sentinel */ >> + }, >> +}; >> +MODULE_DEVICE_TABLE(of, sun8i_ths_id_table); >> + >> +static int sun8i_ths_probe(struct platform_device *pdev) >> +{ >> + struct device_node *np = pdev->dev.of_node; >> + const struct of_device_id *match; >> + struct sun8i_ths_data *data; >> + struct resource *res; >> + int ret; >> + int irq; >> + >> + match = of_match_node(sun8i_ths_id_table, np); > > If you *really* need to (but I still don't really see why), you can > use of_device_get_match_data here. > >> + >> + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); >> + if (!data) >> + return -ENOMEM; >> + >> + data->type = (struct sun8i_ths_type *)match->data; >> + data->pdev = pdev; >> + >> + data->calcell = devm_nvmem_cell_get(&pdev->dev, "calibration"); >> + if (IS_ERR(data->calcell)) { >> + if (PTR_ERR(data->calcell) == -EPROBE_DEFER) >> + return PTR_ERR(data->calcell); > > New line > >> + data->calcell = NULL; /* No calibration register */ > > s/register/data/ ? > >> + } >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + data->regs = devm_ioremap_resource(&pdev->dev, res); >> + if (IS_ERR(data->regs)) { >> + ret = PTR_ERR(data->regs); >> + dev_err(&pdev->dev, >> + "failed to ioremap THS registers: %d\n", ret); >> + return ret; >> + } >> + >> + irq = platform_get_irq(pdev, 0); >> + if (irq < 0) { >> + dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); >> + return irq; >> + } >> + >> + ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, >> + sun8i_ths_irq_thread, IRQF_ONESHOT, >> + dev_name(&pdev->dev), data); > > Why a threaded irq? I thought threaded IRQs are preferred? Other thermal drivers use them too. I am also not really sure thermal_zone_device_update() can even be called in interrupt context. >> + if (ret) >> + return ret; >> + >> + ret = data->type->init(pdev, data); >> + if (ret) >> + return ret; >> + >> + data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, >> + &sun8i_ths_thermal_ops); >> + if (IS_ERR(data->tzd)) { >> + ret = PTR_ERR(data->tzd); >> + dev_err(&pdev->dev, "failed to register thermal zone: %d\n", >> + ret); >> + goto err_deinit; >> + } >> + >> + platform_set_drvdata(pdev, data); >> + return 0; >> + >> +err_deinit: >> + data->type->deinit(data); >> + return ret; >> +} >> + >> +static int sun8i_ths_remove(struct platform_device *pdev) >> +{ >> + struct sun8i_ths_data *data = platform_get_drvdata(pdev); >> + >> + thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); >> + data->type->deinit(data); >> + return 0; >> +} >> + >> +static struct platform_driver sun8i_ths_driver = { >> + .probe = sun8i_ths_probe, >> + .remove = sun8i_ths_remove, >> + .driver = { >> + .name = "sun8i_ths", >> + .of_match_table = sun8i_ths_id_table, >> + }, >> +}; >> + >> +module_platform_driver(sun8i_ths_driver); >> + >> +MODULE_AUTHOR("Josef Gajdusek "); >> +MODULE_DESCRIPTION("Sunxi THS driver"); > > Please change the description here too to match the header. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to > linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. Josef Gajdusek