From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH] iommu/quirk: disable shared EPT for
 Sandybridge and earlier processors.
Date: Wed, 25 Nov 2015 10:28:05 +0000
Message-ID: <56558D35.2040800@citrix.com>
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To: Jan Beulich <JBeulich@suse.com>, "Anshul Makkar anshul.makkar"@citrix.com
Cc: yang.z.zhang@intel.com, Anshul Makkar <anshul.makkar@citrix.com>, kevin.tian@intel.com, xen-devel@lists.xen.org
List-Id: xen-devel@lists.xenproject.org

On 24/11/15 17:41, Jan Beulich wrote:
>>>> On 24.11.15 at 18:17, <Anshul Makkar anshul.makkar@citrix.com> wrote:
>> --- a/xen/drivers/passthrough/vtd/quirks.c
>> +++ b/xen/drivers/passthrough/vtd/quirks.c
>> @@ -320,6 +320,20 @@ void __init platform_quirks_init(void)
>>      /* Tylersburg interrupt remap quirk */
>>      if ( iommu_intremap )
>>          tylersburg_intremap_quirk();
>> +
>> +    /*
>> +     * Disable shared EPT ("sharept") on Sandybridge and older processors
>> +     * by default.
>> +     * SandyBridge has no huge page support for IOTLB which leads to fallback
>> +     * on 4k pages and leads to performance degradation.
>> +     *
>> +     * Shared EPT ("sharept") will be disabled only if user has not
>> +     * provided explicit choice on the command line thus iommu_hap_pt_share is
>> +     * at its initialized value of -1.
>> +     */
>> +    if ( (boot_cpu_data.x86 == 0x06 && (boot_cpu_data.x86_model <= 0x2F ||
>> +          boot_cpu_data.x86_model == 0x36)) && (iommu_hap_pt_share == -1) )
>> +        iommu_hap_pt_share = 0;
> If we really want to do this, then I think we should key this on
> EPT but not VT-d having 2M support, instead of on CPU models.

This check is already performed by vtd_ept_page_compatible()

The problem is that SandyBridge IOMMUs advertise 2M support and do
function with it, but cannot cache 2MB translations in the IOTLBs.

As a result, attempting to use 2M translations causes substantially
worse performance than 4K translations.

~Andrew