From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a1Zpr-0002VR-AR for qemu-devel@nongnu.org; Wed, 25 Nov 2015 08:10:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a1Zpo-0004ly-4A for qemu-devel@nongnu.org; Wed, 25 Nov 2015 08:10:11 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:36360) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a1Zpn-0004lR-VF for qemu-devel@nongnu.org; Wed, 25 Nov 2015 08:10:08 -0500 References: From: Leon Alrae Message-ID: <5655B324.4070409@imgtec.com> Date: Wed, 25 Nov 2015 13:09:56 +0000 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-mips/cpu.h: Fix spell error List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Dongxue Zhang , QEMU Developers Cc: Aurelien Jarno On 25/11/15 12:57, Dongxue Zhang wrote: > CP0IntCtl_IPPC1, the last letter should be 'i', not 'one'. > > Signed-off-by: Dongxue Zhang > --- > target-mips/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target-mips/cpu.h b/target-mips/cpu.h > index 89c01f7..17817c3 100644 > --- a/target-mips/cpu.h > +++ b/target-mips/cpu.h > @@ -358,7 +358,7 @@ struct CPUMIPSState { > #define CP0St_IE 0 > int32_t CP0_IntCtl; > #define CP0IntCtl_IPTI 29 > -#define CP0IntCtl_IPPC1 26 > +#define CP0IntCtl_IPPCI 26 > #define CP0IntCtl_VS 5 > int32_t CP0_SRSCtl; > #define CP0SRSCtl_HSS 26 > Thanks for the patch. I've applied it to post-2.5 target-mips queue. Regards, Leon