From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH] iommu/quirk: disable shared EPT for
 Sandybridge and earlier processors.
Date: Thu, 26 Nov 2015 10:27:13 +0000
Message-ID: <5656DE81.1010509@citrix.com>
References: <1448385479-17614-1-git-send-email-anshul.makkar@citrix.com>
	<5654AF4C02000078000B8A11@prv-mh.provo.novell.com>
	<56558D35.2040800@citrix.com>
	<5655A04202000078000B8E8F@prv-mh.provo.novell.com>
	<5655D021.2010206@citrix.com>
	<5655E41302000078000B919B@prv-mh.provo.novell.com>
	<5655DAC2.6010004@citrix.com>
	<5656D4C802000078000B9427@prv-mh.provo.novell.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <xen-devel-bounces@lists.xen.org>
In-Reply-To: <5656D4C802000078000B9427@prv-mh.provo.novell.com>
List-Unsubscribe: <http://lists.xen.org/cgi-bin/mailman/options/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=unsubscribe>
List-Post: <mailto:xen-devel@lists.xen.org>
List-Help: <mailto:xen-devel-request@lists.xen.org?subject=help>
List-Subscribe: <http://lists.xen.org/cgi-bin/mailman/listinfo/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=subscribe>
Sender: xen-devel-bounces@lists.xen.org
Errors-To: xen-devel-bounces@lists.xen.org
To: Jan Beulich <JBeulich@suse.com>, Anshul Makkar <anshul.makkar@citrix.com>, Malcolm Crossley <malcolm.crossley@citrix.com>
Cc: yang.z.zhang@intel.com, kevin.tian@intel.com, xen-devel@lists.xen.org
List-Id: xen-devel@lists.xenproject.org

On 26/11/15 08:45, Jan Beulich wrote:
>>>> On 25.11.15 at 16:58, <malcolm.crossley@citrix.com> wrote:
>> On 25/11/15 15:38, Jan Beulich wrote:
>>>>>> On 25.11.15 at 16:13, <andrew.cooper3@citrix.com> wrote:
>>>> On 25/11/15 10:49, Jan Beulich wrote:
>>>>> And finally I'm not fully convinced using CPU model info to deduce
>>>>> chipset behavior is entirely correct (albeit perhaps in practice it'll
>>>>> be fine except maybe when running Xen itself virtualized).
>>>> What else would you suggest? I can't think of any better identifying
>>>> information.
>>> Chipset IDs / revisions?
>> In this case the IOMMU is integrated into the Sandybridge-EP processor 
>> itself.
> Which doesn't preclude it to be identified via PCI device ID - after all
> there are dozens of processor integrated PCI devices. Looking at
> one of my systems,
>
> 00:05.0 System peripheral [0880]: Intel Corporation Sandy Bridge Address Map, VTd_Misc, System Management [8086:3c28] (rev 07)
> 80:05.0 System peripheral [0880]: Intel Corporation Sandy Bridge Address Map, VTd_Misc, System Management [8086:3c28] (rev 07)
>
> could be a candidate (we already key a quirk on this device in
> pci_vtd_quirk()).

These are fine for server variants, but not for desktop variants, both
of which we have seen in use.

~Andrew