From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Cooper Subject: Re: [PATCH] x86/PV: hide features dependent on XSAVE when booted with "no-xsave" Date: Mon, 30 Nov 2015 10:46:22 +0000 Message-ID: <565C28FE.80205@citrix.com> References: <5658471802000078000B9A27@prv-mh.provo.novell.com> <56587149.6010909@citrix.com> <565C2C8502000078000BA18C@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1a3LyV-00027v-NO for xen-devel@lists.xenproject.org; Mon, 30 Nov 2015 10:46:27 +0000 In-Reply-To: <565C2C8502000078000BA18C@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: xen-devel , Keir Fraser List-Id: xen-devel@lists.xenproject.org On 30/11/15 10:01, Jan Beulich wrote: >>>> On 27.11.15 at 16:05, wrote: >> On 27/11/15 11:05, Jan Beulich wrote: >>> ... or when the guest has the XSAVE feature hidden by CPUID policy. >>> Not doing so is at best confusing to guests. >>> >>> Signed-off-by: Jan Beulich >> These changes here are an improvement (so I don't object to taking them >> ahead of my fullblown levelling series), but they are incomplete. >> >> xsaveopt, xsavec, xsetbv1, xsaves, avx and mpx depend on xsave. >> fma, fma4, f16c, avx2 and xop depend on avx. > I think the dependencies here are a little fuzzy, and hence I'd > prefer us to not enforce more strict rules than are truly necessary: > > FMA: Neither Intel's SDM nor AMD's PM state any dependency on AVX. > > FMA4, XOP: AMD's PM doesn't state any dependency on AVX. > > AVX2: While Intel's SDM doesn't say so here either, I agree in this case. > > I.e. my view is that FMA{,4} and XOP are all pretty much > independent of AVX, and they e.g. imply by themselves presence of > YMM registers. The AVX feature means several things, and in this case support for VEX encoded instructions. Per SDM Vol 2, Table 2-18, any VEX encoded instruction will unconditionally #UD fault if XCR0[2:1] != '11b' or CR0.OSXSAVE = 0. FMA, FMA4 and XOP may only be VEX encoded, so do explicitly depend on AVX support. (Both the Intel and the AMD manuals are poor at explicitly listing dependencies. I have spent far too much time attempting to reverse engineer the real dependency trees from the information provided.) ~Andrew