From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47833) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a3x5s-0002vF-HK for qemu-devel@nongnu.org; Tue, 01 Dec 2015 21:24:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a3x5p-0003WI-Ds for qemu-devel@nongnu.org; Tue, 01 Dec 2015 21:24:32 -0500 Received: from mail-pa0-x233.google.com ([2607:f8b0:400e:c03::233]:35604) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a3x5p-0003W5-6B for qemu-devel@nongnu.org; Tue, 01 Dec 2015 21:24:29 -0500 Received: by pacej9 with SMTP id ej9so24489463pac.2 for ; Tue, 01 Dec 2015 18:24:28 -0800 (PST) References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> <1447201710-10229-42-git-send-email-benh@kernel.crashing.org> <564A7584.5060605@ozlabs.ru> <1447720804.3729.17.camel@kernel.crashing.org> <20151201064326.GA4903@voom> From: Alexey Kardashevskiy Message-ID: <565E5656.8060200@ozlabs.ru> Date: Wed, 2 Dec 2015 13:24:22 +1100 MIME-Version: 1.0 In-Reply-To: <20151201064326.GA4903@voom> Content-Type: text/plain; charset=koi8-r; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 41/77] ppc/pnv: Add LPC controller and hook it up with a UART and RTC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , Benjamin Herrenschmidt Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 12/01/2015 05:43 PM, David Gibson wrote: > On Tue, Nov 17, 2015 at 11:40:04AM +1100, Benjamin Herrenschmidt wrote: >> On Tue, 2015-11-17 at 11:32 +1100, Alexey Kardashevskiy wrote: >>> On 11/11/2015 11:27 AM, Benjamin Herrenschmidt wrote: >>>> This adds a model of the POWER8 LPC controller. It is then used >>>> by the PowerNV code to attach a UART and RTC, which, with the right >>>> version of OPAL firmware, will provide a working console. >>>> >>>> This version of the LPC controller model doesn't yet implement >>>> support for the SerIRQ deserializer present in the Naples version >>>> of the chip though some preliminary work is there. >>>> >>> >>> Is this LPC controller one per a chip or per a machine? >> >> Per chip but we usually only wire one up per machine. >> >>> In general it is quite nice when "-nodefaults" does not create >>> neither PHB nor LPC so the user can add them manually with parameters >>> different than defaults. >> >> In this case though, PHB and LPC bridges are all part of the P8 chip, >> and I'm trying to represent that topology as best as possible. >> >> I think "-nodefaults" for Pnv should only be about the devices we >> attach to the LPC/PHB not the busses themselves. > > Exactly what is and isn't covered by -nodefaults is a bit of a mess - > part of the topic of my talk at KVM Forum. > > But on the whole I agree with you, since the LPC is part of the P8 > chip, I think it makes sense to include it even with -nodefaults. POWER8 chips all have 8 threads per core but we do not always assume -smt ...,threads=8, how are LPC or PHB different? PHB is more interesting - how is the user supposed to add more? And there always will be the default one which properties are set in a separate way (via -global, not -device). I found it sometime really annoying to debug the existing pseries which always adds a default PHB (I know, this was to make libvirt happy but this is not the case here). Out of curiosity - if we have 2 chips, will the system work if the second chip does not get any LPC or PHB attached? -- Alexey