From: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
To: Mark Brown <broonie@kernel.org>
Cc: <stefan@agner.ch>, <linux-spi@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Bhuvanchandra <bhuvanchandra.dv@toradex.com>
Subject: Re: [PATCH] spi-fsl-dspi: Fix CTAR Register access
Date: Thu, 10 Dec 2015 10:12:25 +0530 [thread overview]
Message-ID: <566902B1.2080503@toradex.com> (raw)
In-Reply-To: <20151209204103.GJ5727@sirena.org.uk>
On 12/10/2015 02:11 AM, Mark Brown wrote:
> On Wed, Dec 09, 2015 at 11:51:39AM +0530, Bhuvanchandra DV wrote:
>> DSPI instances in Vybrid have a different amount of chip selects
>> and CTARs (Clock and transfer Attributes Register). In case of
>> DSPI1 we only have 2 CTAR registers and 4 CS. In present driver
>
> This doesn't apply against, current code - please check and resend.
Will check and resend.
>
--
Best regards,
Bhuvan
prev parent reply other threads:[~2015-12-10 4:42 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-09 6:21 [PATCH] spi-fsl-dspi: Fix CTAR Register access Bhuvanchandra DV
2015-12-09 6:21 ` Bhuvanchandra DV
[not found] ` <1449642099-13045-1-git-send-email-bhuvanchandra.dv-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
2015-12-09 20:41 ` Mark Brown
2015-12-09 20:41 ` Mark Brown
2015-12-10 4:42 ` Bhuvanchandra DV [this message]
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