From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sylwester Nawrocki Subject: Re: DT soundcard driver with special clock routing Date: Thu, 10 Dec 2015 18:13:33 +0100 Message-ID: <5669B2BD.6010100@samsung.com> References: <5669A8DE.7060702@barix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) by alsa0.perex.cz (Postfix) with ESMTP id 4D645265182 for ; Thu, 10 Dec 2015 18:15:31 +0100 (CET) Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZ500DO0JXST9B0@mailout2.w1.samsung.com> for alsa-devel@alsa-project.org; Thu, 10 Dec 2015 17:15:28 +0000 (GMT) In-reply-to: <5669A8DE.7060702@barix.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org To: Petr Kulhavy Cc: alsa-devel@alsa-project.org List-Id: alsa-devel@alsa-project.org On 10/12/15 17:31, Petr Kulhavy wrote: > Hi, > > I'm developing a DT-based driver for an ARM SoC device with the > following special clock routing: > > - WM8758 codec attached to the CPU DAI via I2S > - the codec is I2S clock master > - the CPU feeds the codec with 12MHz clock (outside of the I2S) > - the codec converts the 12MHz internally to 48kHz*256 or 44.1kHz *256 > clock and provides it to I2S as MCLK > > So the special set-up needed here is that the codec needs to be > configured to: > a) generate the proper MCLK > b) enable the respective GPIO pin as clock output > > What is the best way of representing this set-up using device tree? > I'm wondering if this can be done by adding a specific option in the > codec DT binding for enabling the clock output and then use the simple > audio card. > Or do I need to write a specific soundcard driver that sets up the codec > registers? I would like to avoid that if possible and use existing code... > > What would you recommend? I assume when the clock enable/disable code is not there it could be added to the codec driver, e.g. like in case of max98090. The clock source just needs to be exposed as a common clock object. As an example of similar setup you could take a look at arch/arm/boot/dts/exynos4412-odroid-common.dts. The difference was that in case of Odroid the clock was generated by a PLL inside a SoC, then it was routed to I2S which fed the clock to the codec through the SoC's io pin. The codec was I2S master and the I2S IP block was actually a source of its main ("mclk") clock. I hope this helps. -- Regards, Sylwester